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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Bus Control and Input/Output  
0 = Associated pin is a high-impedance input  
1 = Associated pin is an output  
PE[1:0] are associated with XIRQ and IRQ and cannot be configured as  
outputs. These pins can be read regardless of whether the alternate  
interrupt functions are enabled.  
This register is not in the map in peripheral mode and expanded modes  
while the EME control bit is set.  
Read and write anytime.  
BIT 7  
6
5
4
3
2
1
BIT 0  
NDBE  
CGMTE  
PIPOE  
NECLK  
LSTRE  
RDWE  
CALE  
DBENE  
Normal  
Expanded  
RESET:  
0
0
0
0
0
0
0
0
Special  
Expanded  
RESET:  
RESET:  
RESET:  
0
1
1
0
1
0
1
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
Peripheral  
Normal  
single chip  
Special  
single chip  
RESET:  
0
0
1
0
1
1
0
0
PEAR — Port E Assignment Register  
$000A  
The PEAR register is used to choose between the general-purpose I/O  
functions and the alternate bus control functions of port E. When an  
alternate control function is selected, the associated DDRE bits are  
overridden.  
The reset condition of this register depends on the mode of operation  
because bus-control signals are needed immediately after reset in some  
modes.  
In normal single-chip mode, no external bus control signals are needed  
so all of port E is configured for general-purpose I/O.  
Advance Information  
92  
68HC(9)12D60 — Rev 4.0  
Bus Control and Input/Output  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
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