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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Operating Modes and Resource Mapping  
Special Expanded Narrow Mode — This mode can be used  
for emulation of normal expanded narrow mode. Ports A and B  
are used for the16-bit address bus. Port A is used as the data  
bus, multiplexed with addresses. In this mode, 16-bit data is  
presented one byte at a time, the high byte followed by the low  
byte. The address is automatically incremented on the second  
cycle.  
Special Peripheral Mode — The CPU is not active in this  
mode. An external master can control on-chip peripherals for  
testing purposes. It is not possible to change to or from this  
mode without going through reset. Background debugging  
should not be used while the MCU is in special peripheral  
mode as internal bus conflicts between BDM and the external  
master can cause improper operation of both modes.  
5.4 Background Debug Mode  
Background debug mode (BDM) is an auxiliary operating mode that is  
used for system development. BDM is implemented in on-chip hardware  
and provides a full set of debug operations. Some BDM commands can  
be executed while the CPU is operating normally. Other BDM  
commands are firmware based, and require the BDM firmware to be  
enabled and active for execution.  
In special single-chip mode, BDM is enabled and active immediately out  
of reset. BDM is available in all other operating modes, but must be  
enabled before it can be activated. BDM should not be used in special  
peripheral mode because of potential bus conflicts.  
Once enabled, background mode can be made active by a serial  
command sent via the BKGD pin or execution of a CPU12 BGND  
instruction. While background mode is active, the CPU can interpret  
special debugging commands, and read and write CPU registers,  
peripheral registers, and locations in memory.  
While BDM is active, the CPU executes code located in a small on-chip  
ROM mapped to addresses $FF20 to $FFFF, and BDM control registers  
are accessible at addresses $FF00 to $FF06. The BDM ROM replaces  
Advance Information  
76  
68HC(9)12D60 — Rev 4.0  
Operating Modes and Resource Mapping  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
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