TL431, A, B Series
Figure 31. Simplified TL431 Device Model
V
CC
R
L
C
L
Input
3
15 k
Cathode
9.0
F
Go
1.0 mho
R
10 M
P2
Ref
V
ref
1
1.78 V
C
G
P1
20 pF
M
C
+
P2
R
R
1.0 M
ref
16
GM
0.265 pF
R
15.9 k
Z1
500 k
–
8.25 k
Anode
2
Figure 32. Example 1
Circuit Open Loop Gain Plot
Note that the transfer function now has an extra pole
formed by the load capacitance and load resistance.
Note that the crossover frequency in this case is about
250 kHz, having a phase margin of about –46 degrees.
Therefore, instability of this circuit is likely.
TL431 OPEN–LOOP VOLTAGE GAIN VERSUS FREQUENCY
60
50
40
30
Figure 33. Example 2
Circuit Open Loop Gain Plot
TL431 OPEN–LOOP BODE PLOT WITH LOAD CAP
80
20
10
0
60
40
20
–10
–20
1
2
3
4
5
6
7
10
10
10
10
10
10
10
f, FREQUENCY (Hz)
Example 2.
= 7.5 mA, R = 2.2 k , C = 0.01 F. Cathode tied to
0
I
C
L
L
reference input pin. An examination of the data sheet stability
boundary curve (Figure 15) shows that this value of load
capacitance and cathode current is on the boundary. Define
the transfer gain.
–20
1
2
3
4
5
6
10
10
10
10
10
10
f, FREQUENCY (Hz)
With three poles, this system is unstable. The only hope
for stabilizing this circuit is to add a zero. However, that can
only be done by adding a series resistance to the output
capacitance, which will reduce its effectiveness as a noise
filter. Therefore, practically, in reference voltage applications,
the best solution appears to be to use a smaller value of
capacitance in low noise applications or a very large value to
provide noise filtering and a dominant pole rolloff of the
system.
The DC gain is:
G
G R
GoR
M GM
L
(2.323)(1.0 M)(1.25 )(2200)
6389
76 dB
The resulting open loop Bode plot is shown in Figure 33.
The asymptotic plot may be expressed as the following
equation:
1
jf
500 kHz
jf
8.0 kHz 60 kHz 7.2 kHz
Av
615
1
jf
1
1
jf
12
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