Freescale Semiconductor, Inc.
PCB Layout
Pin No.
Pin Name
Description
STATUS
ST
P1
1 thru 3
—
No internal connection. Leave
unconnected.
P0
4
5
6
ST
Logic input pin used to initiate
self–test.
V
SS
V
OUT
A/D IN
R
C
0.1 µF
V
Output voltage of the accelerome-
ter.
C
1 kΩ
0.01 µF
OUT
V
SS
V
DD
C
0.1 µF
V
DD
—
No internal connection. Leave
unconnected.
V
RH
C
0.1 µF
7
8
V
The power supply ground.
The power supply input.
SS
V
DD
9 thru 13
Trim pins
Used for factory trim. Leave
unconnected.
POWER SUPPLY
14 thru 16
—
No internal connection. Leave
unconnected.
Figure 5. Recommend PCB Layout for Interfacing
Accelerometer to Microcontroller
NOTES:
•
•
•
Use a 0.1 µF capacitor on V
source.
to decouple the power
DD
Physical coupling distance of the accelerometer to the
microcontroller should be minimal.
Place a ground plane beneath the accelerometer to reduce
noise, the ground plane should be attached to all of the
open ended terminals shown in Figure 4.
6
MMA2201D
STATUS
V
DD
LOGIC
INPUT
4
8
ST
V
R1
1 kΩ
•
Use an RC filter of 1 kΩ and 0.01 µF on the output of the
accelerometer to minimize clock noise (from the switched
capacitor filter circuit).
5
OUTPUT
SIGNAL
V
DD
OUT
C1
0.1 µF
C2
0.01 µF
•
•
•
PCB layout of power and ground should not couple power
supply noise.
7
V
SS
Accelerometer and microcontroller should not be a high
current path.
A/Dsamplingrateandanyexternalpowersupplyswitching
frequency should be selected such that they do not inter-
fere with the internal accelerometer sampling frequency.
This will prevent aliasing errors.
Figure 4. SOIC Accelerometer with Recommended
Connection Diagram
2–46
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Motorola Sensor Device Data
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