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MC74LCX245DW 参数 Datasheet PDF下载

MC74LCX245DW图片预览
型号: MC74LCX245DW
PDF下载: 下载PDF文件 查看货源
内容描述: 低压CMOS八路收发器 [LOW-VOLTAGE CMOS OCTAL TRANSCEIVER]
分类和应用:
文件页数/大小: 8 页 / 161 K
品牌: MOTOROLA [ MOTOROLA, INC ]
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage CMOS Octal
Transceiver
With 5V-Tolerant Inputs and Outputs
(3-State, Non-Inverting)
The MC74LCX245 is a high performance, non–inverting octal
transceiver operating from a 2.7 to 3.6V supply. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5V allows MC74LCX245 inputs to be
safely driven from 5V devices. The MC74LCX245 is suitable for memory
address driving and all TTL level bus oriented transceiver applications.
Current drive capability is 24mA at both A and B ports. The
Transmit/Receive (T/R) input determines the direction of data flow
through the bi–directional transceiver. Transmit (active–HIGH) enables
data from A ports to B ports; Receive (active–LOW) enables data from B
to A ports. The Output Enable input, when HIGH, disables both A and B
ports by placing them in a HIGH Z condition.
MC74LCX245
LOW–VOLTAGE CMOS
OCTAL TRANSCEIVER
20
1
DW SUFFIX
PLASTIC SOIC
CASE 751D–04
Designed for 2.7 to 3.6V VCC Operation
5V Tolerant — Interface Capability With 5V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0V
LVTTL Compatible
LVCMOS Compatible
24mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10µA)
Substantially Reduces System Power Requirements
20
1
20
1
M SUFFIX
PLASTIC SOIC EIAJ
CASE 967–01
SD SUFFIX
PLASTIC SSOP
CASE 940C–03
Latchup Performance Exceeds 500mA
ESD Performance: Human Body Model >2000V; Machine Model >200V
20
1
DT SUFFIX
PLASTIC TSSOP
CASE 948E–02
Pinout: 20–Lead
(Top View)
VCC
20
OE
19
B0
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
PIN NAMES
Pins
OE
T/R
A0–A7
B0–B7
Function
Output Enable Input
Transmit/Receive Input
Side A 3–State Inputs or 3–State
Outputs
Side B 3–State Inputs or 3–State
Outputs
1
T/R
2
A0
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
GND
9/95
©
Motorola, Inc. 1996
1
REV 3