Freescale Semiconductor, Inc.
FLASH Memory
4.3 Functional Description
The FLASH memory is an array of 32,256 bytes with one byte of block
protection and an additional 52 bytes of user vectors. An erased bit
reads as a logic 1 and a programmed bit reads as a logic 0.
Memory in the FLASH array is organized into rows within pages. There
are two rows of memory per page with 64 bytes per row. The minimum
erase block size is a single page,128 bytes. Programming is performed
on a per-row basis, 64 bytes at a time. Program and erase operations
are facilitated through control bits in the FLASH Control Register
(FLCR). Details for these operations appear later in this section.
The FLASH memory map consists of:
•
•
•
•
$8000–$FDFF: User Memory (32,256 bytes)
$FF80: FLASH Block Protect Register (FLBPR)
$FF88: FLASH Control Register (FLCR)
$FFCC–$FFFF: these locations are reserved for user-defined
interrupt and reset vectors (Please see
Vector Addresses and
Priority
on page 59 for details)
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NOTE:
A security feature prevents viewing of the FLASH contents.
(1)
4.4 FLASH Control and Block Protect Registers
The FLASH array has two registers that control its operation, the FLASH
Control Register (FLCR) and the FLASH Block Protect Register
(FLBPR).
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Advance Information
64
FLASH Memory
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68HC908AZ32A — Rev 0.0
MOTOROLA
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