Parallel Input/Output
4.9.1 PORTG — Port G data register
Address bit 7
Port G data (PORTG)
$007E
PG7
bit 6
PG6
bit 5
PG5
bit 4
PG4
bit 3
PG3
bit 2
PG2
bit 1
PG1
bit 0
State
on reset
PG0 undefined
The bits may be read and written at any time and are not affected by
reset.
4.9.2 DDRG — Data direction register for port G
Address bit 7
Data direction G (DDRG)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$007F DDG7 DDG6 DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 0000 0000
DDG[7:0] — Data direction for port G
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
4.10 Port H
Port H is an 8-bit bidirectional port, with both data and data direction
registers. In addition to their I/O capability, port H pins are shared with
SCI/MI BUS and PWM functions, as shown in the following table.
Alternate
function
PW1
PW2
PW3
PW4
RXD2
TXD2
RXD3
TXD3
Pin
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
See
Timing System
for more information.
See
Serial Communications
Interface (SCI)
and
Motorola
Interconnect Bus (MI BUS)
On reset the pins are configured as general purpose high-impedance
inputs with selectable internal resistors. The internal resistors are pull-
Technical Data
82
Parallel Input/Output
MC68HC11P2 — Rev 1.0
MOTOROLA
MOTOROLA [ MOTOROLA, INC ]
