FE — Framing Error
0 = No framing error on the received data
1 = Framing error or break occurred on the received data.
PF — Parity Error
0 = No parity error on the received data
1 = Parity error occurred on the received data.
D.4.7 SCDR — SCI Data Register
$YFFC0E
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
RESET:
0
0
0
0
0
0
0
U
U
U
U
U
U
U
U
U
SCDR consists of two data registers located at the same address. RDR is a read-only
register that contains data received by the SCI serial interface. Data comes into the
receive serial shifter and is transferred to RDR. TDR is a write-only register that con-
tains data to be transmitted. Data is first written to TDR, then transferred to the transmit
serial shifter, where additional format bits are added before transmission. R[7:0]/T[7:0]
contain either the first eight data bits received when SCDR is read, or the first eight
data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is con-
figured for 9-bit operation. When the SCI is configured for 8-bit operation, R8/T8 have
no meaning or effect.
D
D.4.8 PORTQS — Port QS Data Register
$YFFC15
15
8
7
6
5
4
3
2
1
0
NOT USED
PQS7 PQS6 PQS5 PQS4 PQS3 PQS2 PQS1 PQS0
RESET:
0
0
0
0
0
0
0
0
PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data
present on the pins. To avoid driving undefined data, first write a byte to PORTQS,
then configure DDRQS.
D.4.9 PQSPAR — PORT QS Pin Assignment Register
DDRQS — PORT QS Data Direction Register
$YFFC16
$YFFC17
15
0
14
13
12
11
10
0
9
8
7
6
5
4
3
2
1
0
PQSPA6 PQSPA5 PQSPA4 PQSPA3
PQSPA1 PQSPA0 DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Clearing a bit in PQSPAR assigns the corresponding pin to general-purpose I/O; set-
ting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI.
MOTOROLA
D-30
REGISTER SUMMARY
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
