FPWMA — Force PWMA Value
0 = Normal PWMA operation.
1 = The value of F1A is driven out on the PWMA pin, regardless of the state of
PPROUT.
FPWMB — Force PWMB Value
0 = Normal PWMB operation.
1 = The value of F1B is driven out on the PWMB pin.
PPROUT — PWM Clock Output Enable
0 = Normal PWM operation on PWMA.
1 = TCNT clock driven out PWMA pin.
PPR[2:0] — PWM Prescaler/PCLK Select
This field selects one of seven prescaler taps or PCLK to be PWMCNT input.
PPR[2:0]
System Clock
Divide-by Factor
000
001
010
011
100
101
110
111
2
4
8
D
16
32
64
128
PCLK
SFA — PWMA Slow/Fast Select
0 = PWMA period is 256 PWMCNT increments long.
1 = PWMA period is 32768 PWMCNT increments long.
SFB — PWMB Slow/Fast Select
0 = PWMB period is 256 PWMCNT increments long.
1 = PWMB period is 32768 PWMCNT increments long.
The following table shows a range of PWM output frequencies using a 16.78-MHz sys-
tem clock and 20.97 system clock.
PPR
[2:0]
000
001
010
011
100
101
110
111
Prescaler Tap
SFA/B = 0
SFA/B = 1
16.78 MHz
16.78 MHz
20.97 MHz
16.78 MHz
20.97 MHz
41 kHz
20.97 MHz
320 Hz
160 Hz
80.0 Hz
40.0 Hz
20.0 Hz
10.0 Hz
5.0 Hz
Div 2 = 8.39 MHz
Div 4 = 4.19 MHz
Div 8 = 2.10 MHz
Div 2 = 10.5 MHz
Div 4 = 5.25 MHz
Div 8 = 2.62 MHz
32.8 kHz
16.4 kHz
8.19 kHz
4.09 kHz
2.05 kHz
1.02 kHz
512 Hz
256 Hz
128 Hz
64.0 Hz
32.0 Hz
16.0 Hz
8.0 Hz
20.5 kHz
10.2 kHz
5.15 kHz
2.56 kHz
1.28 kHz
641 Hz
Div 16 = 1.05 MHz Div 16 = 1.31 MHz
Div 32 = 524 kHz
Div 64 = 262 kHz
Div 32 = 655 kHz
Div 64 = 328 kHz
Div 128 = 131 kHz Div 128 = 164 kHz
PCLK PCLK
4.0 Hz
PCLK/256
PCLK/256
PCLK/32768 PCLK/32768
F1A — Force Logic Level One on PWMA
0 = Force logic level zero output on PWMA pin.
1 = Force logic level one output on PWMA pin.
MC68331
USER’S MANUAL
REGISTER SUMMARY
MOTOROLA
D-11
MOTOROLA [ MOTOROLA ]
