FRZ[1:0] — FREEZE Response
FRZ1 is not used; FRZ0 encoding determines response to the IMB FREEZE signal.
0 = Ignore IMB FREEZE signal
1 = Freeze the current state of the GPT
STOPP — Stop Prescaler
0 =Normal operation
1 =Stop prescaler and pulse accumulator from incrementing. Ignore changes to in-
put pins.
INCP — Increment Prescaler
0 =Has no meaning
1 =If STOPP is asserted, increment prescaler once and clock input synchronizers
once.
SUPV — Supervisor/Unrestricted Data Space
0 =Registers with access controlled by the SUPV bit are accessible from either the
user or supervisor privilege level.
1 =Registers with access controlled by the SUPV bit are restricted to supervisor
access only.
D
IARB[3:0] — Interrupt Arbitration
Each module that generates interrupts must have an IARB value. IARB values are
used to arbitrate between interrupt requests of the same priority.
D.2.2 GPTMTR — GPT Module Test Register (Reserved)
$YFF902
This address is currently unused and returns zeros when read. It is reserved for GPT
factory test.
D.2.3 ICR — GPT Interrupt Configuration Register
$YFF904
15
12
11
0
10
8
7
4
0
3
0
2
0
1
0
0
0
IPA
IPL
0
IVBA
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ICR fields determine internal and external interrupt priority, and provide the upper nib-
ble of the interrupt vector number supplied to the CPU when an interrupt is acknowl-
edged.
IPA — Interrupt Priority Adjust
Specifies which of the 11 internal GPT interrupt sources is assigned highest priority.
IPL — Interrupt Priority Level
Specifies the priority level of GPT interrupt requests.
IVBA — Interrupt Vector Base Address
Contains the most significant nibble of interrupt vector numbers supplied by the GPT.
MC68331
REGISTER SUMMARY
MOTOROLA
D-5
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
