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MC68331CFC16 参数 Datasheet PDF下载

MC68331CFC16图片预览
型号: MC68331CFC16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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System Clock  
SCI Baud Clock Rate = ------------------------------------  
32 × SCBR  
where SCBR is in the range {1, 2, 3,..., 8191}.  
The SCI receiver operates asynchronously. An internal clock is necessary to synchro-  
nize with an incoming data stream. The SCI baud clock generator produces a receive  
time (RT) sampling clock with a frequency 16 times that of the SCI baud clock. The  
SCI determines the position of bit boundaries from transitions within the received  
waveform, and adjusts sampling points to the proper positions within the bit period.  
6.4.3.4 Parity Checking  
The parity type (PT) bit in SCCR1 selects either even (PT = 0) or odd (PT = 1) parity.  
PT affects received and transmitted data. The parity enable (PE) bit in SCCR1 deter-  
mines whether parity checking is enabled (PE = 1) or disabled (PE = 0). When PE is  
set, the MSB of the data in a frame is used for the parity function. For transmitted data,  
a parity bit is generated; for received data, the parity bit is checked. When parity check-  
ing is enabled, the parity flag (PF) in the SCI status register (SCSR) is set if a parity  
error is detected.  
Enabling parity affects the number of data bits in a frame, which can in turn affect  
frame size. Table 6-6 shows possible data and parity formats.  
6
Table 6-6 Effect of Parity Checking on Data Size  
M
0
0
1
1
PE  
0
Result  
8 Data Bits  
1
7 Data Bits, 1 Parity Bit  
9 Data Bits  
0
1
8 Data Bits, 1 Parity Bit  
6.4.3.5 Transmitter Operation  
The transmitter consists of a serial shifter and a parallel data register (TDR) located in  
the SCI data register (SCDR). The serial shifter cannot be directly accessed by the  
CPU. The transmitter is double-buffered, which means that data can be loaded into  
the TDR while other data is shifted out. The transmitter enable (TE) bit in SCCR1 en-  
ables (TE = 1) and disables (TE = 0) the transmitter.  
Shifter output is connected to the TXD pin while the transmitter is operating (TE = 1,  
or TE = 0 and transmission in progress). Wired-OR operation should be specified  
when more than one transmitter is used on the same SCI bus. The wired-OR mode  
select bit (WOMS) in SCCR1 determines whether TXD is an open-drain (wired-OR)  
output or a normal CMOS output. An external pull-up resistor on the TXD pin is nec-  
essary for wired-OR operation. WOMS controls TXD function whether the pin is used  
for SCI transmissions (TE = 1) or as a general-purpose I/O pin.  
Data to be transmitted is written to TDR, then transferred to the serial shifter. The  
transmit data register empty (TDRE) flag in SCSR shows the status of TDR. When  
TDRE = 0, TDR contains data that has not been transferred to the shifter. Writing to  
MC68331  
QUEUED SERIAL MODULE  
MOTOROLA  
6-27  
USER’S MANUAL