MC33171 MC33172 MC33174
APPLICATIONS INFORMATION – CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
voltage to approach within millivolts of V . For sink currents
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MC33171/72/74 amplifier family is similar to low power op
amp products utilizing JFET input devices, these amplifiers
offer additional advantages as a result of the PNP transistor
differential inputs and an all NPN transistor output stage.
Because the input common mode voltage range of this
(> 0.4 mA), diode D3 clamps the voltage across R4. Thus the
negative swing is limited by the saturation voltage of Q15,
plus the forward diode drop of D3 (≈V
+1.0 V). Therefore
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an unprecedented peak–to–peak output voltage swing is
possible for a given supply voltage as indicated by the output
swing specifications.
input stage includes the V
operation is feasible to as low as 3.0 V with the common
mode input voltage at ground potential.
potential, single supply
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If the load resistance is referenced to V
instead of
CC
ground for single supply applications, the maximum possible
output swing can be achieved for a given supply voltage. For
light load currents, the load resistance will pull the output to
The input stage also allows differential input voltages up to
±44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
V
during the positive swing and the output will pull the load
CC
between V
and V
supply voltages as shown by the
resistance near ground during the negative swing. The load
resistance value should be much less than that of the
feedback resistance to maximize pull–up capability.
CC
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maximum rating table. In practice, although not
recommended, the input voltages can exceed the V
CC
voltage by approximately 3.0 V and decrease below the V
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voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
Because the PNP output emitter–follower transistor has
been eliminated, the MC33171/72/74 family offers a 15 mA
minimum current sink capability, typically to an output voltage
up to 5.0 mA of current from V
through either inputs’
of (V
+1.8 V). In single supply applications the output can
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clamping diode without damage or latching, but phase
reversal may again occur. If at least one input is within the
common mode input voltage range and the other input is
within the maximum input voltage range, no phase reversal
will occur. If both inputs exceed the upper common mode
input voltage limit, the output will be forced to its lowest
voltage state.
directly source or sink base current from a common emitter
NPN transistor for current switching applications.
In addition, the all NPN transistor output stage is inherently
faster than PNP types, contributing to the bipolar amplifier’s
improved gain bandwidth product. The associated high
frequency low output impedance (200 Ω typ @ 1.0 MHz)
allows capacitive drive capability from 0 pF to 400 pF without
oscillation in the noninverting unity gain configuration. The
60°C phase margin and 15 dB gain margin, as well as the
general gain and phase characteristics, are virtually
independent of the source/sink output swing conditions. This
allows easier system phase compensation, since output
swing will not be a phase consideration. The AC
characteristics of the MC33171/72/74 family also allow
excellent active filter capability, especially for low voltage
single supply applications.
Although the single supply specification is defined at 5.0 V,
these amplifiers are functional to at least 3.0 V @ 25°C.
However slight changes in parametrics such as bandwidth,
slew rate, and DC gain may occur.
If power to this integrated circuit is applied in reverse
polarity, or if the IC is installed backwards in a socket, large
unlimited current surges will occur through the device that
may result in device destruction.
As usual with most high frequency amplifiers, proper lead
dress, component placement and PC board layout should
be exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted input/output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole for optimum frequency response, but also minimizes
extraneous “pick up” at this node. Supply decoupling with
adequate capacitance immediately adjacent to the supply pin
is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
Since the input capacitance associated with the small
geometry input device is substantially lower (0.8 pF) than that
of a typical JFET (3.0 pF), the frequency response for a given
input source resistance is greatly enhanced. This becomes
evident in D–to–A current to voltage conversion applications
where the feedback resistance can form a pole with the input
capacitance of the op amp. This input pole creates a 2nd
Order system with the single pole op amp and is therefore
detrimental to its settling time. In this context, lower input
capacitance is desirable especially for higher values of
feedback resistances (lower current DACs). This input pole
can be compensated for by creating a feedback zero with a
capacitance across the feedback resistance, if necessary, to
reduce overshoot. For 10 kΩ of feedback resistance, the
MC33171/72/74 family can typically settle to within 1/2 LSB
of 8 bits in 4.2 µs, and within 1/2 LSB of 12 bits in 4.8 µs for
a 10 V step. In a standard inverting unity gain fast settling
configuration, the symmetrical slew rate is typically
± 2.1 V/µs. In the classic noninverting unity gain
configuration the typical output positive slew rate is also
2.1 V/µs, and the corresponding negative slew rate will
usually exceed the positive slew rate as a function of the fall
time of the input waveform.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. A 10 kΩ load resistance can typically swing within 0.8 V
of the positive rail (V ) and negative rail (V ), providing a
CC
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28.4 Vpp swing from ±15 V supplies. This large output swing
becomes most noticeable at lower supply voltages.
The positive swing is limited by the saturation voltage of
the current source transistor Q7, the V
of the NPN pull–up
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transistor Q17, and the voltage drop associated with the
short circuit resistance, R5. For sink currents less than
0.4 mA, the negative swing is limited by the saturation
voltage of the pull–down transistor Q15, and the voltage drop
across R4 and R5. For small valued sink currents, the above
voltage drops are negligible, allowing the negative swing
The output of any one amplifier is current limited and thus
protected from a direct short to ground. However, under such
conditions, it is important not to allow the device to exceed
the maximum junction temperature rating. Typically for ±15 V
supplies, any one output can be shorted continuously to
ground without exceeding the maximum temperature rating.
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MOTOROLA ANALOG IC DEVICE DATA
MOTOROLA [ MOTOROLA ]
