DI1 – DIn
Data Input Pins
off while the + 5 V is on and the off supply is a low impedance
to ground, the diode D1 will prevent current flow through the
internal diode.
These are the high impedance digital input pins to the driv-
ers. Input voltage levels on these pins are LSTTL compatible
and must be between V and GND. A weak pull–up on
each input sets all unused DI pins to V , causing the corre-
The diode D2 is used as a voltage clamp, to prevent V
from drifting positive to V , in the event that power is re-
CC
SS
CC
moved from V
SS
SS
approximately 3 kΩ, this pin will be pulled to V
circuitry causing excessive current in the V
If by design, neither of the above conditions are allowed to
exist, then the diodes D1 and D2 are not required.
(Pin 12). If V
impedance from the V
power is removed, and the
SS
pin to ground is greater than
CC
sponding unused driver outputs to be at V
.
SS
by internal
CC
pin.
CC
Tx1 – TXn
Transmit Data Output Pins
These are the EIA–232–E transmit signal output pins,
which swing from V to V . A logic 1 at the DI input causes
DD
SS
ESD PROTECTION
the corresponding Tx output to swing to V . A logic 0 at the
SS
DI input causes the corresponding Tx out to swing to V
ESD protection on IC devices that have their pins accessi-
ble to the outside world is essential. High static voltages ap-
plied to the pins when someone touches them either directly
or indirectly can cause damage to gate oxides and transistor
junctions by coupling a portion of the energy from the I/O pin
to the power supply buses of the IC. This coupling will usually
occur through the internal ESD protection diodes. The key to
protecting the IC is to shunt as much of the energy to ground
as possible before it enters the IC. Figure 4 shows a tech-
nique which will clamp the ESD voltage at approximately
± 15 V using the MMBZ15VDLT1. Any residual voltage which
appears on the supply pins is shunted to ground through the
capacitors C1 – C3. This scheme has provided protection to
the interface part up to ± 10 kV, using the human body model
test.
.
DD
The actual levels and slew rate achieved will depend on the
output loading (R C ).
L
L
APPLICATION INFORMATION
POWER SUPPLY CONSIDERATIONS
Figure 4 shows a technique to guard against excessive de-
vice current.
The diode D1 prevents excessive current from flowing
through an internal diode from the V
pin to the V
pin
CC
by approximately 0.6 V or greater. This high
DD
when V
< V
DD
CC
current condition can exist for a short period of time during
power up/down. Additionally, if the + 12 V supply is switched
+ 12 V
D1
MMBZ15VDLT1 x 10
+ 5 V
1N4001
C1
V
V
CC
DD
1
24
C2
1N4001
Rx1
Tx1
2
3
23 DO1
22 DI1
R
D
Rx2
Tx2
4
5
21 DO2
20 DI2
R
R
R
R
D
D
Rx3
Tx3
Rx4
Tx4
6
7
8
9
19 DO3
18 DI3
17 DO4
16 DI4
15 DO5
D
Rx5 10
Tx5 11
14 DI5
D
V
12
13 GND
SS
C3
D2
1N5818
– 12 V
Figure 4.
MC145403•MC145404•MC145405•MC145408
MOTOROLA
6
MOTOROLA [ MOTOROLA ]
