V62C1801024L(L)
DC Operating Characteristics (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
-70
-85
-100
-150
Parameter
Sym Test Conditions
Unit
Min Max Min Max Min Max Min Max
Vcc = Max,
Vin = Gnd to Vcc
-
-
-
1
1
3
-
-
-
1
1
3
-
-
-
1
1
3
-
-
-
1
1
3
mA
Input Leakage Current
II
LI
CE1 = VIH or CE2 = VIL
Vcc= Max, VOUT = Gnd to Vcc
mA
Output Leakage
Current
IILO
CE1 = VIL , CE2 = VIH
VIN=VIHorVIL,IOUT=0mA
mA
Operating Power
Supply Current
ICC
CE1 = VIL , CE2 = VIH
IOUT = 0mA,
Min Cycle, 100% Duty
-
-
25
3
-
-
20
3
-
-
15
3
-
-
15
3
mA
mA
ICC1
Average Operating
Current
CE1 = 0.2V,
CE2 = Vcc - 0.2V
ICC2
IOUT = 0mA,
Cycle Time=1ms, 100% Duty
CE1 = VIH or CE2 = VIL
-
-
0.5
5
-
-
0.5
5
-
-
0.5
5
-
-
0.5
5
mA
Standby Power Supply ISB
Current (TTL Level)
CE1 > Vcc - 0.2V or
CE2 < 0.2V, f = 0
VIN < 0.2V or
L
mA
Standby Power Supply ISB1
Current (CMOS Level)
-
-
1
0.4
-
-
-
1
0.4
-
-
-
1
0.4
-
-
-
1
0.4
-
mA
V
VIN > Vcc- 0.2V
IOL = 2 mA
LL
Output Low Voltage
Output High Voltage
VOL
VOH
IOH = -1 mA
1.6
1.6
1.6
1.6
V
Capacitance (f = 1MHz, TA = 250C)
Parameter*
Input Capacitance
Symbol
Cin
Test Condition
Max
7
Unit
pF
V = 0V
in
I/O Capacitance
CI/O
V = V = 0V
8
pF
in
out
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing
Reference Level
0.4V to 1.6V
5ns
TTL
CL
*
50% of input level
(VIL + VIH)/2
Output Load Condition
70ns/85 ns CL = 30pf + 1TTL Load
Load 100ns/150 ns CL = 100pf + 1TTL Load
Figure A.
* Including Scope and Jig Capacitance
4
REV. 1.1 April 2001 V62C1801024L(L)