V62C1162048L(L)
Timing Waveform of Read Cycle 1
(Address Controlled)
t
RC
Address
t
OH
Data Out
t
AA
Data Valid
Previous Data Valid
Timing Waveform of Read Cycle 2
t
RC
Address
t
AA
CE
t
ACE
t
LZ(4,5)
t
BA
t
BLZ(4,5)
t
OE
High-Z
t
OLZ
t
HZ(3,4,5)
t
BHZ(3,4,5)
(BLE/BHE)
t
OHZ
t
OH
Data Valid
OE
Data Out
Notes
(Read Cycle)
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit condition referenced to V
OH
or V
OL
levels.
4. At any given temperature and voltage condition
t
HZ
(max.) is less than
t
LZ
(min.) both for a given device and from device to
device.
5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
6. Device is continuously selected with CE = V
IL
.
7. Address valid prior to coincident with CE transition Low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
9. For test conditions, see
AC Test Condition,
Figure A.
6
REV. 1.2
May
2001 V62C1162048L(L)
MOSEL [ MOSEL VITELIC, CORP ]
