MOSEL VITELIC
V58C265404S
Data Strobe Preamble and Postamble Timings for DDR Read Cycles
(CAS Latency = 2; Burst Length = 2)
T4
T0
T1
T2
T3
CK, CK
READ
NOP
NOP
NOP
Command
t
(max)
RPRE
t
(min)
RPRE
t
(min)
RPST
DQS
DQ
t
(max)
RPST
t
(min)
DQSQ
D
D
0
1
t
(max)
DQSQ
Consecutive Burst Read Operation and Effects on the Data Strobe Preamble and Postamble
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK
NOP
Read
NOP
Read
NOP
NOP
NOP
NOP
NOP
Command
DQS
A
B
D0 D1 D2 D3 D0 D1 D2 D3
DQ
A
A
A
A
B
B
B
B
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK
NOP
Read
NOP
Read
NOP
NOP
NOP
NOP
NOP
Command
DQS
A
B
D0 D1 D2 D3
D0 D1 D2 D3
B B B B
DQ
A
A
A
A
V58C265404S Rev. 1.4 January 2000
11
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