V58C2128(804/404/164)S
Block Diagram
Column decoder
Sense amplifier & I(O) bus
Bank 0
Column decoder
Sense amplifier & I(O) bus
Bank 1
Column decoder
Sense amplifier & I(O) bus
Bank 2
Column decoder
Sense amplifier & I(O) bus
CKE
CK, CK
DLL
Strobe
Gen.
Data Strobe
DQS
Capacitance*
T
A
= 0 to 70°C, V
CC
= 2.5V
±
0.2V, f = 1 Mhz
Input Capacitance
BA0, BA1, CKE, CS, RAS, (CAS,
A0-A11, WE)
Input Capacitance (CK, CK)
Data & DQS I/O Capacitance
Input Capacitance (DM)
Symbol
Min
C
INI
C
IN2
C
OUT
C
IN3
2
2
4
4
Absolute Maximum Ratings*
Max Unit
3.0
3.0
5
5.0
pF
pF
pF
pF
*Note: Capacitance is sampled and not 100% tested.
Operating temperature range ..................0 to 70 °C
Storage temperature range ................-55 to 150 °C
V
DD
Supply Voltage Relative to V
SS
.....-1V to +3.6V
V
DDQ
Supply Voltage Relative to V
SS
......................................................-1V to +3.6V
VREF and Inputs Voltage Relative to V
SS
......................................................-1V to +3.6V
I/O Pins Voltage Relative to V
SS
.......................................... -0.5V to V
DDQ
+0.5V
Power dissipation .......................................... 1.6 W
Data out current (short circuit) ...................... 50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
V58C2128(804/404/164)S Rev. 1.6 March 2002
5
QFC
RAS
CAS
WE
DM
CK
CK
CS
CILETIV LESO M
8M x 16
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Bank 3
4096 x 256
x 32 bit
4096 x 256
x 32 bit
4096 x 256
x 32 bit
4096 x 256
x 32 bit
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
15
MOSEL [ MOSEL VITELIC, CORP ]
