欢迎访问ic37.com |
会员登录 免费注册
发布采购

V54C365804VD 参数 Datasheet PDF下载

V54C365804VD图片预览
型号: V54C365804VD
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能143/133/125 MHz的3.3伏8M ×8的同步DRAM 4组X的2Mbit ×8 [HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8]
分类和应用: 动态存储器
文件页数/大小: 54 页 / 772 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
 浏览型号V54C365804VD的Datasheet PDF文件第2页浏览型号V54C365804VD的Datasheet PDF文件第3页浏览型号V54C365804VD的Datasheet PDF文件第4页浏览型号V54C365804VD的Datasheet PDF文件第5页浏览型号V54C365804VD的Datasheet PDF文件第6页浏览型号V54C365804VD的Datasheet PDF文件第7页浏览型号V54C365804VD的Datasheet PDF文件第8页浏览型号V54C365804VD的Datasheet PDF文件第9页  
V54C365804VD(L)
HIGH PERFORMANCE 143/133/125 MHz
3.3 VOLT 8M X 8 SYNCHRONOUS DRAM
4 BANKS X 2Mbit X 8
PRELIMINARY
s
4 banks x 2Mbit x 8 organization
s
High speed data transfer rates up to 143 MHz
s
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s
Single Pulsed RAS Interface
s
Data Mask for Read/Write Control
s
Four Banks controlled by BA0 & BA1
s
Programmable CAS Latency: 2, 3
s
Programmable Wrap Sequence: Sequential
or Interleave
s
Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
s
Multiple Burst Read with Single Write Operation
s
Automatic and Controlled Precharge Command
s
Random Column Address every CLK (1-N Rule)
s
Suspend Mode and Power Down Mode
s
Auto Refresh and Self Refresh
s
Refresh Interval: 4096 cycles/64 ms
s
Available in 54 Pin 400 mil TSOP-II
s
LVTTL Interface
s
Single +3.3 V
±0.3
V Power Supply
CILETIV LESOM
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
7
143MHz
7 ns
5.4 ns
5.5 ns
75
133MHz
7.5 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
8
125 MHz
8 ns
7 ns
7 ns
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
Features
Description
The V54C365804VD(L) is a four bank Synchro-
nous DRAM organized as 4 banks x 2Mbit x 8. The
V54C365804VD(L) achieves high speed data trans-
fer rates up to 143 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
143 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T
Access Time (ns)
7
Power
8
75
8PC
Std.
L
Temperature
Mark
Blank
V54C365804VD(L) Rev. 0.9 September 2001
1