MOSEL VITELIC
V54C333322V
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
don’t care
don’t care
DIN A
0
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
0
1
2
3
tCK2, I/O’s
CAS latency = 3
DIN A
0
don’t care
DOUT B
3
0
1
2
tCK3, I/O’s
Input data must be removed from the I/O’s at least one clock
cycle before the Read dataAPpears on the outputs to avoid
data contention.
7. Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
BANK A
ACTIVE
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t
COMMAND
Auto-Precharge
t
WR
RP
CAS latency = 2
DIN A0
DIN A0
DIN A1
t
I/O’s
*
*
t
WR
RP
CAS latency = 3
DIN A1
I/O’s
Begin Autoprecharge
*
Bank can be reactivated after trp
V54C333322V Rev. 2.0 May 2000
17