V54C3256(16/80/40)4V(T/S/B)
CILETIV LESOM
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
V 54 C 3 25640 4 V A L T
Device
Number
Special
Feature
Speed
6 ns
7 ns
8 ns
TSOP Component
Package
L=Low Power
4 Banks
Component Rev Level A=0.17um
B=0.14um
V=LVTTL
Description
TSOP-II
Pkg.
T
Pin Count
54
C=CMOS Family
3.3V, LVTTL INTERFACE
64Mx4(8K Refresh)
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
CLK
CKE
CS
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
V
CC
NC
V
CCQ
NC
I/O
1
V
SSQ
NC
NC
V
CCQ
NC
I/O
2
V
SSQ
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356404V-01
V
SS
NC
V
SSQ
NC
I/O
4
V
CCQ
NC
NC
V
SSQ
NC
I/O
3
V
CCQ
NC
V
SS
NC
DQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
I/O
1
–I/O
4
DQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
5
MOSEL [ MOSEL VITELIC, CORP ]
