V54C316162VC
CILETIV LESOM
Pin
CLK
CKE
Signal Pin Description
Name
Clock Input
Clock Enable
Input Function
System clock input. Active on the positive rising edge to sample all inptus
Activates the CLK signal when high and deactivates the CLK when low.
CKE low initiates the power down mode, suspend mode, or the self
refresh mode
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQMi
Latches row addresses on the positive edge of CLK with RAS low.
Enables row access & precharge
Latches column addresses on the positive edge of CLK with CAS low.
Enables column access
Enables write operation
During a bank activate command, A
0
-A
10
defines the row address.
During a read or write command, A
0
-A
7
defines the column address. In
addition to the column address A
10
is used to invoke auto precharge BA
define the bank to be precharged. A
10
is low, auto precharge is disabled
during a precharge cycle, If A
10
is high, both bank will be precharged ,
if A
10
is low, the BA is used to decide which bank to precharge. If A
10
is
high, all banks will be precharged.
Selects which bank to activate. BA low select bank A and high selects
bank B
Data inputs/output are multiplexed on the same pins
Makes data output Hi-Z. Blocks data input when DQM is active
Power Supply. +3.3V ± 0.3V/ground
Provides isolated power/ground to DQs for improved noise immunity
CS
Chip Select
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
A
0
-A
10
Write Enable
Address
BA
Bank Select
I/O
1
-I/O
16
UDQM, LDQM
VDD/VSS
VDDQ/VSSQ
NC
Data Input/Output
Data Input/Output Mask
Power Supply/Ground
Data Output Power/Ground
No Connection
V54C316162VC Rev. 1.4 December 2001
4
MOSEL [ MOSEL VITELIC, CORP ]
