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V54C3128804VAT 参数 Datasheet PDF下载

V54C3128804VAT图片预览
型号: V54C3128804VAT
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能133分之143 / 125MHz的3.3伏16M ×8的同步DRAM 4组X的4Mbit ×8 [HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8]
分类和应用: 动态存储器
文件页数/大小: 43 页 / 362 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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MOSEL VITELIC  
V54C3128804VAT  
Clock Enable (CKE) Truth Table:  
CKE  
n-1  
CKE  
n
STATE(n)  
CS  
RAS  
CAS  
WE  
Addr ACTION  
6
Self-Refresh  
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID  
EXIT Self-Refresh, Idle after tRC  
EXIT Self-Refresh, Idle after tRC  
ILLEGAL  
ILLEGAL  
ILLEGAL  
L
X
X
X
X
NOP (Maintain Self-Refresh)  
Power-Down  
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID  
EXIT Power-Down, > Idle.  
EXIT Power-Down, > Idle.  
ILLEGAL  
ILLEGAL  
ILLEGAL  
L
X
X
X
X
NOP (Maintain Low-Power Mode)  
All. Banks  
Idle  
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
X
X
X
H
H
H
L
L
L
X
X
X
H
H
L
H
L
L
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
Refer to the function truth table  
Enter Power- Down  
Enter Power- Down  
ILLEGAL  
ILLEGAL  
ILLEGAL  
Enter Self-Refresh  
ILLEGAL  
NOP  
7
X
X
Abbreviations:  
RA = Row Address  
BS = Bank Address  
AP = Auto Precharge  
CA = Column Address  
Notes for SDRAM function truth table:  
1. Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preceding clock cycle.  
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank.  
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.  
4. NOP to bank precharging or in Idle state. May precharge bank(s) indicated by BS (andAP).  
5. Illegal if any bank is not Idle.  
6. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any  
command other than EXIT.  
7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.  
8. Must be legal command as defined in the SDRAM function truth table.  
V54C3128804VAT Rev. 1.4 November 2000  
41  
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