V54C3128(16/80/40)4V(T/S)
V 54 C 3 12880 4 V A L T
Mosel Vitelic
Manufactured
Speed
6 ns
Device
7 ns
8 ns
Number
SYNCHRONOUS
DRAM FAMILY
Special
Feature
Component
Package
C=CMOS Family
3.3V, LVTTL INTERFACE
16Mx8(4K Refresh)
Description Pkg.
TSOP-II
Pin Count
L=Low Power
T
54
4 Banks
Component Rev Level
V=LVTTL
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
CLK
Clock Input
CKE
Clock Enable
V
I/O
CCQ
NC
I/O
2
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
CC
CS
Chip Select
2
I/O
V
1
8
V
3
SSQ
RAS
Row Address Strobe
Column Address Strobe
Write Enable
4
NC
CAS
5
I/O
V
7
V
V
6
SSQ
NC
I/O
3
CCQ
NC
CCQ
WE
7
NC
8
I/O
V
6
A0–A11
BA0, BA1
I/O1–I/O8
DQM
VCC
Address Inputs
Bank Select
9
SSQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
I/O
4
I/O
V
5
Data Input/Output
Data Mask
V
SSQ
NC
CCQ
NC
V
NC
WE
CAS
RAS
CS
BA0
BA1
V
CC
SS
NC
Power (+3.3V)
Ground
DQM
CLK
CKE
NC
VSS
VCCQ
VSSQ
NC
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
A
A
A
A
A
A
A
V
11
9
A
10
A
0
A
1
A
2
A
3
CC
8
7
6
5
4
V
SS
V54C3128(16/80/40)4V(T/S) Rev.1.2 August 2002
4
MOSEL [ MOSEL VITELIC, CORP ]
