MOSEL VITELIC
V53C818H
OE signal has no effect on any data stored in the
output latches. A WE low level can also disable the
output drivers when CAS is low. During a Write
cycle, if WE goes low at a time in relationship to
CAS that would normally cause the outputs to be
active, it is necessary to use OE to disable the
output drivers prior to the WE low transition to allow
Extended Data Output Page Mode
EDO Page operation permits all 512 columns
within a selected row of the device to be randomly
accessed at a high data rate. Maintaining RAS low
while performing successive CAS cycles retains the
row address internally and eliminates the need to
reapply it for each cycle. The column address buffer
acts as a transparent or flow-through latch while
CAS is high. Thus, access begins from the
occurrence of a valid column address rather than
Data In Setup Time (t ) to be satisfied.
DS
Power-On
from the falling edge of CAS, eliminating t
and t
After application of the V
supply, an initial
ASC
T
CC
from the critical timing path. CAS latches the
address into the column address buffer. During
EDO operation, Read, Write, Read-Modify-Write or
Read-Write-Read cycles are possible at random
addresses within a row. Following the initial entry
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
cycle into Hyper Page Mode, access is t
or t
During Power-On, the V current requirement of
CAA
CAP
CC
the V53C818H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
controlled. If the column address is valid prior to the
rising edge of CAS, the access time is referenced to
device will go into an active cycle and I will exhibit
the CAS rising edge and is specified by t
. If the
CC
CAP
current transients. It is recommended that RAS and
column address is valid after the rising CAS edge,
access is timed from the occurrence of a valid
CAS track with V or be held at a valid V during
CC
IH
Power-On to avoid current surges.
address and is specified by t
. In both cases, the
CAA
falling edge of CAS latches the address and
enables the output.
Table 1. V53C818H Data Output
Operation for Various Cycle Types
EDO provides a sustained data rate of 83 MHz for
applications that require high bandwidth such as bit-
mapped graphics or high-speed signal processing.
The following equation can be used to calculate the
maximum data rate:
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
512
Data Rate = ----------------------------------------
WE-Controlled Write
Cycle (Late Write)
OE Controlled. High
OE = High-Z I/Os
t
+ 511 × t
RC
PC
Read-Modify-Write
Cycles
Data from Addressed
Memory Cell
Data Output Operation
The V53C818H Input/Output is controlled by OE,
CAS, WE and RAS. A RAS low transition enables
the transfer of data to and from the selected row
address in the Memory Array. A RAS high transition
disables data transfer and latches the output data if
the output is enabled. After a memory cycle is
initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level
disables the I/O path and the output driver if it is
enabled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output
drivers. The output drivers, when otherwise
enabled, can be disabled by holding OE high. The
EDO Read Cycle
Data from Addressed
Memory Cell
EDO Write Cycle
(Early Write)
High-Z
EDO Read-Modify-
Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
V53C818H Rev. 1.2 May 1997
16
MOSEL [ MOSEL VITELIC, CORP ]
