MOSEL VITELIC
V53C818H
Waveforms of EDO-Page-Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
t
t
RP
RAS
V
V
IH
IL
RAS
t
CSH
t
t
t
RSH
PC
PC
t
CRP
t
t
t
t
t
t
t
CP
RCD
CAS
CP
CAS
CP
CAS
V
V
IH
IL
UCAS, LCAS
t
t
t
CAR
AR
t
RAD
t
t
t
t
t
t
t
CAH
ASR
RAH
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
ADDRESS
t
RCH
t
RCS
t
t
WCH
WCS
V
V
IH
IL
WE
t
CAA
t
t
CAA
t
CAP
t
RAC
t
t
DH
CAC
t
DS
CAC
t
OE
V
V
IH
IL
OE
I/O
t
COH
V
OH
VALID
DATA OUT
VALID
DATA OUT
VALID
DATA IN
V
OL
Don’t Care
Undefined
Functional Description
Read Cycle
The V53C818H is a CMOS dynamic RAM
optimized for high data bandwidth, low power
applications. It is functionally similar to a traditional
dynamic RAM. The V53C818H reads and writes
data by multiplexing an 18-bit address into a 10-bit
row and a 9-bit column address. The row address is
latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS
operation. The column address must be held for a
minimum specified by t . Data Out becomes valid
only when t
satisifed. As a result, the access time is dependent
on the timing relationships between these
parameters. For example, the access time is limited
AR
, t
, t
and t
are all
OAC
RAC
CAA
CAC
by t
when t
, t
and t
are all satisfied.
CAA
RAC CAC
OAC
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column
address is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be
ended or aborted before the minimum t
expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
time has
RAS
the minimum precharge time t /t has elapsed.
RP CP
the high state and t
must be satisfied.
OED
V53C818H Rev. 1.2 May 1997
15
MOSEL [ MOSEL VITELIC, CORP ]
