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V53C8129H35 参数 Datasheet PDF下载

V53C8129H35图片预览
型号: V53C8129H35
PDF下载: 下载PDF文件 查看货源
内容描述: 超高性能, 128K X 8EDO页模式的CMOS动态RAM [ULTRA-HIGH PERFORMANCE, 128K X 8EDO PAGE MODE CMOS DYNAMIC RAM]
分类和应用:
文件页数/大小: 18 页 / 200 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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MOSEL VITELIC  
V53C8129H  
AC Characteristics  
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted  
AC Test conditions, input pulse levels 0 to 3V  
35  
40  
45  
50  
JEDEC  
#
1
2
3
4
5
6
7
8
9
Symbol  
tRL1RH1  
tRL2RL2  
tRH2RL2  
tRL1CH1  
tCL1CH1  
tRL1CL1  
tWH2CL2  
tAVRL2  
Symbol Parameter  
tRAS RAS Pulse Width  
tRC  
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes  
35 75K 40 75K 45 75K 50 75K ns  
Read or Write Cycle Time  
RAS Precharge Time  
CAS Hold Time  
70  
25  
35  
7
75  
25  
40  
8
80  
25  
45  
9
90  
30  
50  
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRP  
tCSH  
tCAS  
tRCD  
tRCS  
tASR  
tRAH  
tASC  
tCAH  
CAS Pulse Width  
RAS to CAS Delay  
16  
0
23  
17  
0
28  
18  
0
32  
19  
0
36  
Read Command Setup Time  
Row Address Setup Time  
Row Address Hold Time  
Column Address Setup Time  
Column Address Hold Time  
4
0
0
0
0
tRL1AX  
6
7
8
9
10 tAVCL2  
11 tCL1AX  
0
0
0
0
4
5
6
7
12 tCL1RH1(R) tRSH (R) RAS Hold Time (Read Cycle)  
14  
5
14  
5
15  
5
15  
5
13 tCH2RL2  
14 tCH2WX  
tCRP  
tRCH  
CAS to RAS Precharge Time  
Read Command Hold Time Referenced  
to CAS  
0
0
0
0
5
5
15 tRH2WX  
tRRH  
Read Command Hold Time Referenced  
to RAS  
0
8
0
9
0
0
ns  
16 tOEL1RH2  
17 tGL1QV  
18 tCL1QV  
19 tRL1QV  
20 tAVQV  
21 tCL1QX  
22 tCH2QZ  
23 tRL1AX  
24 tRL1AV  
tROH  
tOAC  
tCAC  
tRAC  
tCAA  
tLZ  
RAS Hold Time Referenced to OE  
Access Time from OE  
10  
10  
ns  
ns  
ns  
12  
12  
35  
18  
12  
12  
40  
20  
13  
13  
45  
22  
14  
14  
50  
24  
Access Time from CAS (EDO)  
Access Time from RAS  
6, 7  
ns 6, 8, 9  
ns 6, 7, 10  
Access Time from Column Address  
CAS to Low-Z Output  
0
0
0
0
0
0
0
0
ns  
ns  
ns  
ns  
ns  
ns  
16  
16  
tHZ  
Output buffer turn-off delay time  
Column Address Hold Time from RAS  
RAS to Column Address Delay Time  
6
6
7
8
tAR  
28  
11  
12  
12  
0
30  
12  
12  
12  
0
35  
13  
13  
13  
0
40  
14  
14  
14  
0
tRAD  
17  
20  
23  
26  
11  
25 tCL1RH1(W) tRSH (W) RAS or CAS Hold Time in Write Cycle  
26 tWL1CH1  
27 tWL1CL2  
28 tCL1WH1  
29 tWL1WH1  
30 tRL1WH1  
31 tWL1RH1  
tCWL  
tWCS  
tWCH  
tWP  
Write Command to CAS Lead Time  
Write Command Setup Time  
Write Command Hold Time  
ns 12, 13  
5
5
6
7
ns  
ns  
ns  
ns  
Write Pulse Width  
5
5
6
7
tWCR  
tRWL  
Write Command Hold Time from RAS  
Write Command to RAS Lead Time  
28  
12  
30  
12  
35  
13  
40  
14  
V53C8129H Rev. 1.3 July 1997  
5
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