MO SEL VITELIC
V53C316405A
they were not equal, the I/O would indicate a “0”. The
WCBR cycle (WE, CAS before RAS) puts the device
into test mode. To exit from test mode, a “CAS be-
fore RAS refresh”, “RAS only refresh” or “Hidden re-
fresh” can be used.Refresh during test mode
operation can be performed by normal read cycles or
by WCBR refresh cycles.
Row addresses A0 through A11 have to kept high
to perform a testmode entry cycle. All other address-
es are don’t care.
Test Mode
As the V53C316405A is organized internally as
4M x 4-bits, a test mode cycle using 4:1 compression
can be used to improve test time. Note that in the 4M
x 4 version the test time is reduced by 1/4 for a N test
pattern.
In a test mode “write” the data from each I/O pin is
written into four 1M blocks simultaneously (all “1” s
or all “0” s). In test mode “read” each I/O output is
used for indicating the test mode result. If the internal
four bits are equal, the I/O would indicate a “1”. If
Block Diagram in Test Mode
A0C,A1C
A0C,A1C
1 M Block
Vcc
Normal
1 M Block
Normal
I/O 1
I/O 1
1 M Block
Test
Test
1 M Block
Vss
Vcc
A0C,A1C
A0C,A1C
1 M Block
Normal
Normal
1 M Block
I/O 2
I/O 2
1 M Block
Test
Test
1 M Block
Vss
Vcc
A0C,A1C
A0C,A1C
1 M Block
Normal
1 M Block
Normal
I/O 3
1 M Block
Test
I/O 3
Test
1 M Block
Vss
Vcc
A0C,A1C
A0C,A1C
1 M Block
Normal
1 M Block
Normal
I/O 4
I/O 4
Vss
1 M Block
Test
Test
1 M Block
V53C316405A Rev. 1.2 March 1998
22
MOSEL [ MOSEL VITELIC, CORP ]
