MO SEL VITELIC
V53C316405A
Notes:
1) All voltages are referenced to V
.
SS
2)
3)
I
I
, I
, I
and I
depend on cycle rate.
CC1 CC3 CC4
CC5
and I
depend on output loading. Specified values are obtained with the output open.
CC1
CC4
4) Address can be changed once or less while RAS = V . In case of ICC4 it can be changed once or less during a
IL
EDO page mode cycle
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum
of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume t = 2 ns.
T
7)
V
and V
are reference levels for measuring timing of input signals. Transition times are also measured
IH (min.)
IL (max.)
between V and V .
IH
IL
8) Measured with the specified current load and 100 pF at V = 0.8 V and V = 2.0 V. Access time is determined by
OL
OH
the latter of t
, t
, t
,t
, t
. t
is measured from tristate.
RAC CAC CAA CPA OEA CAC
9) Operation within the t
limit ensures that t
can be met. t
is specified as a reference point
RCD (max.)
RAC (max.)
RCD (max.)
only. If t
is greater than the specified t
limit, then access time is controlled by t
.
RCD
RCD (max.)
CAC
10) Operation within the t
limit ensures that t
can be met. t
is specified as a reference point
RAD (max.)
RAC (max.)
RAD (max.)
only. If t
is greater than the specified t
limit, then access time is controlled by t
.
RAD
RAD (max.)
CAA
11) Either t
12)
or t
must be satisfied for a read cycle.
RCH
RRH
t
, t
define the time at which the output achieves the open-circuit conditions and are not referenced
OFF (max.) OEZ (max.)
to output voltage levels. t
is referenced from the rising edge of RAS or CAS, whichever occurs last.
OFF
13) Either t
14) Either t
or t
must be satisfied.
must be satisfied.
DZC
CDD
DZO
or t
ODD
15)
t
, t
, t
and t
are not restrictive operating parameters. They are included in the data sheet as electrical
WCS RWD CWD
AWD
characteristics only. If t
> t
, the cycle is an early write cycle and data out pin will remain open-circuit
WCS
WCS (min.)
(high impedance) through the entire cycle; if t
> t
, t
> t
and t
> t
, the cycle
RWD
RWD (min.) CWD
CWD (min.)
AWD
AWD (min.)
is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions
is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CASleading edge in early write cycles and to the WE leading edge in read-
write cycles.
V53C316405A Rev. 1.2 March 1998
8
MOSEL [ MOSEL VITELIC, CORP ]
