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V53C16258SHT30 参数 Datasheet PDF下载

V53C16258SHT30图片预览
型号: V53C16258SHT30
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能256K ×16 EDO页模式的CMOS动态RAM可选自刷新 [HIGH PERFORMANCE 256K X 16 EDO PAGE MODE CMOS DYNAMIC RAM OPTIONAL SELF REFRESH]
分类和应用: 内存集成电路光电二极管动态存储器
文件页数/大小: 20 页 / 560 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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MO SEL VITELIC  
V53C16258H  
AC Characteristics (Cont’d)  
25  
(100 MHz)  
30  
35  
40  
45  
50  
#
Symbol Parameter  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes  
54  
55  
56  
t
t
t
OE High Pulse Width  
4
5
8
10  
10  
10  
ns  
ns  
OEP  
T
Transition Time (Rise and Fall)  
Refresh Interval (512 Cycles)  
1.5 50 1.5 50 1.5 50 1.5 50 1.5 50 1.5 50  
15  
17  
8
8
8
8
8
8
ms  
REF  
Optional Self Refresh  
57  
58  
59  
60  
t
t
t
t
RAS Pulse Width During Self  
Refresh  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
µs  
ns  
ns  
µs  
18  
18  
18  
18  
RASS  
RAS Precharge Time During  
Self Refresh  
RPS  
CAS Hold Time Width During  
Self Refresh  
CHS  
CHD  
CAS Low Time During Self  
Refresh  
Notes:  
1.  
I
is dependent on output loading when the device output is selected. Specified I (max.) is measured with the  
C
C
C
C
output open.  
2.  
I
is dependent upon the number of address transitions. Specified I (max.) is measured with a maximum of two  
CC  
CC  
transitions per address cycle in EDO Page Mode.  
3. Specified V (min.) is steady state operating. During transitions, V (min.) may undershoot to –1.0 V for a period  
IL  
IL  
not to exceed 20 ns. All AC parameters are measured with V (min.) V and V (max.) V  
.
IL  
SS  
IH  
CC  
4.  
t
(max.) is specified for reference only. Operation within t  
(max.) limits insures that t  
(max.) and t  
RCD  
RCD  
RAC CAA  
(max.) can be met. If t  
is greater than the specified t  
(max.), the access time is controlled by t  
and t  
.
RCD  
RCD  
CAA  
CAC  
5. Either t  
or t  
must be satisified for a Read Cycle to occur.  
RRH  
RCH  
6. Measured with a load equivalent to one TTL input and 50 pF.  
7. Access time is determined by the longest of t , t and t  
.
CAP  
CAA CAC  
8. Assumes that t  
t  
(max.). If t  
is greater than t  
(max.), t  
will increase by the amount that t  
RAD  
RAD  
RAD  
RAD  
RAC RAD  
exceeds t  
(max.).  
RAD  
9. Assumes that t  
t  
(max.). If t  
(max.).  
is greater than t  
(max.), t  
will increase by the amount that t  
RCD  
RCD  
RCD  
RCD  
RAC RCD  
exceeds t  
(max.).  
RCD  
10. Assumes that t  
t  
RAD  
RAD  
11. Operation within the t  
(max.) limit ensures that t  
(max.) can be met. t  
(max.) is specified as a reference  
RAD  
RAC  
RAD  
point only. If t  
is greater than the specified t  
(max.) limit, the access time is controlled by t  
and t  
.
RAD  
RAD  
CAA  
CAC  
12.  
13.  
14.  
t
t
t
, t  
, t  
and t  
are not restrictive operating parameters.  
WCS RWD AWD  
CWD  
(min.) must be satisfied in an Early Write Cycle.  
WCS  
and t are referenced to the latter occurrence of CAS or WE.  
DS  
DH  
15. t is measured between V (min.) and V (max.). AC-measurements assume t = 3 ns.  
T
IH  
IL  
T
16. Assumes a three-state test load (5 pF and a 500 Ohm Thevenin equivalent).  
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without  
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.  
18. One CBR refresh or complete set of row refreah cycles must be completed upon exiting Self Refreah Mode.  
V53C16258H Rev. 3.8 November 1999  
7