V437464E24V
Notes:
1. The specified values are valid when addresses are changed no more than once during t (min.) and when No
CK
Operation commands are registered on every rising clock edge during t (min). Values are shown per module
RC
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during t (min.).
RC
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have V = 0.4V and V = 2.4V with the timing referenced to the 1.4V crossover point. The transition
IL
IH
time is measured between V and V . All AC measurements assume t = 1 ns with the AC output load circuit
IH
IL
T
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V
tCH
2.4V
0.4V
50 Ohm
CLOCK
tCL
Z=50 Ohm
tT
I/O
tSETUP tHOLD
50 pF
1.4V
INPUT
tAC
tAC
I/O
tLZ
tOH
50 pF
Measurement conditions for
tac and toh
1.4V
OUTPUT
tHZ
5. If clock rising time is longer than 1 ns, a time (t /2 -0.5) ns has to be added to this parameter.
T
6. Rated at 1.5V
7. If t is longer than 1 ns, a time (t -1) ns has to be added to this parameter.
T
T
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up” the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to t is satisfied once the Self Refresh Exit command
RC
is registered.
10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
t
is equivalent to t
+ t
.
RP
DAL
DPL
V437464E24V Rev. 1.0 January 2002
10
MOSEL [ MOSEL VITELIC, CORP ]
