V437464C24V
written into the E
2
PROM device during module pro-
duction using a serial presence detect protocol (I
2
C
synchronous 2-wire bus)
A serial presence detect storage device –
2
PROM – is assembled onto the module. Informa-
E
tion about the module configuration, speed, etc. is
CILETIV LESOM
SPD-Table
0
1
2
3
4
Memory Type
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CS Latencies
WE Latencies
24
25
26
27
Serial Presence Detect Information
Byte Num-
ber
Function Described
Number of SPD bytes
Total bytes in Serial PD
Hex Value
SPD Entry Value
128
256
SDRAM
13
11
-75PC
80
08
04
0D
0B
-75
80
08
04
0D
0B
-10PC
80
08
04
0D
0B
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x4
SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (continued)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay from Back to Back
Random Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
1
72
0
LVTTL
7.5 ns/10.0 ns
5.4 ns/6.0 ns
ECC
Self-Refresh, 7.8µs
x4
n/a / x4
t
ccd
= 1 CLK
1, 2, 4, 8
4
CL = 2/3
CS Latency = 0
WL = 0
Registered/Buffered
Vcc tol ± 10%
7.5ns/10.0ns
01
48
00
01
75
54
02
82
04
04
01
01
48
00
01
75
54
02
82
04
04
01
01
48
00
01
A0
60
02
82
04
04
01
0F
04
06
01
01
1F
0E
75
0F
04
06
01
01
1F
0E
A0
0F
04
06
01
01
1F
0E
A0
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency
=2
Maximum Data Access Time from Clock for
CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at
CL = 1
Minimum Row Precharge Time
5.4ns/6.0ns
54
54
60
Not Supported
Not Supported
00
00
00
00
00
00
15 ns/20 ns
0F
14
14
V437464C24V Rev. 1.0 January 2002
4
MOSEL [ MOSEL VITELIC, CORP ]
