V4374128C24V
CILETIV LESOM
28
29
30
31
32
33
34
35
36-61
62
63
64
65-71
72
73-90
91-92
93
94
95-98
99-125
126
127
128+
SPD Revision
Reserved
Reserved
SPD-Table: (Continued)
Byte Num-
ber
Function Described
Minimum Row Active to Row Active Delay
t
RRD
Minimum RAS to CAS Delay t
RCD
Minimum RAS Pulse Width t
RAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Fu-
ture)
Revision 2/1.2
Hex Value
SPD Entry Value
14 ns/15 ns/16 ns
-75PC
0F
-75
0F
-10PC
0F
15 ns/20 ns
42 ns/45 ns
512 MByte
1.5 ns/2.0 ns
0.8 ns/1.0 ns
1.5 ns/2.0 ns
0.8 ns/1.0 ns
0F
2A
80
15
08
15
08
00
14
2D
80
15
08
15
08
00
14
2D
80
20
10
20
10
00
02
69
02
AD
40
00
12
1A
40
00
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
Module Part Number (ASCII)
PCB Identification Code
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
V4374128C24V
Mosel Vitelic
40
00
00
64
8D
00
00
64
8D
00
00
64
8D
00
Intel Specification for Frequency
Unused Storage Location
V4374128C24V Rev. 1.1 January 2002
6
MOSEL [ MOSEL VITELIC, CORP ]
