欢迎访问ic37.com |
会员登录 免费注册
发布采购

V437316S04VXTG-10PC 参数 Datasheet PDF下载

V437316S04VXTG-10PC图片预览
型号: V437316S04VXTG-10PC
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3伏16M X 72高性能非缓冲ECC SDRAM模块 [3.3 VOLT 16M x 72 HIGH PERFORMANCE UNBUFFERED ECC SDRAM MODULE]
分类和应用: 动态存储器
文件页数/大小: 12 页 / 314 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
 浏览型号V437316S04VXTG-10PC的Datasheet PDF文件第4页浏览型号V437316S04VXTG-10PC的Datasheet PDF文件第5页浏览型号V437316S04VXTG-10PC的Datasheet PDF文件第6页浏览型号V437316S04VXTG-10PC的Datasheet PDF文件第7页浏览型号V437316S04VXTG-10PC的Datasheet PDF文件第9页浏览型号V437316S04VXTG-10PC的Datasheet PDF文件第10页浏览型号V437316S04VXTG-10PC的Datasheet PDF文件第11页浏览型号V437316S04VXTG-10PC的Datasheet PDF文件第12页  
V437316S04V
CILETIV LESOM
AC Characteristics
T
A
= 0° to 70°C; V
SS
= 0V; V
CC
= 3.3V
±
0.3V, t
T
= 1 ns (Continued)
Limit Values
-75PC
#
5
6
-75
Min.
2.5
1
-10PC
Symbol
t
CL
t
T
Parameter
Clock Low Pulse Width
Transition Tim
Min.
2.5
1
Max.
Max.
Min.
2.5
1
Max.
Unit
ns
ns
Note
Setup and Hold Times
7
8
9
10
11
12
t
IS
t
IH
t
CKS
t
CKH
t
RSC
t
SB
Input Setup Time
Input Hold Time
Input Setup Time
CKE Hold Time
Mode Register Set-up Time
Power Down Mode Entry Time
1.5
0.8
1.5
0.8
15
0
7.5
1.5
0.8
1.5
0.8
15
0
7.5
1.5
0.8
1.5
0.8
15
0
7.5
ns
ns
ns
ns
ns
ns
5
5
5
5
Common Parameters
13
14
15
16
17
t
RCD
t
RP
t
RAS
t
RC
t
RRD
t
CCD
Row to Column Delay Time
Row Precharge Time
Row Active Time
Row Cycle Time
Activate(a) to Activate(b) Command
Period
CAS(a) to CAS(b) Command Period
15
20
42
60
14
100K
20
20
45
70
15
100K
20
20
45
70
20
100K
ns
ns
ns
ns
ns
6
6
6
6
6
18
1
1
1
CLK
Refresh Cycle
19
20
t
REF
t
SREX
Refresh Period (4096 cycles)
Self Refresh Exit Time
64
64
64
ms
ns
10
10
10
Read Cycle
21
22
23
24
t
OH
t
LZ
t
HZ
t
DQZ
Data Out Hold Time
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
3
0
3
2
7.5
3
0
3
2
7.5
3
0
3
2
8
ns
ns
ns
CLK
7
2
Write Cycle
25
26
t
WR
t
DQW
Write Recovery Time
DQM Write Mask Latency
2
0
2
0
1
0
CLK
CLK
V437316S04V Rev. 1.0 December 2001
8