V436632Z24V
CILETIV LESO M
SPD-Table
Byte
Number
28
Hex Value
Function Described
Minimum Row Active to Row Active Delay
t
RRD
Minimum RAS to CAS Delay t
RCD
Minimum RAS Pulse Width t
RAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Fu-
ture)
SPD Revision
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
Module Part Number (ASCII)
PCB Identification Code
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
1 = US, 2 = Taiwan
V436632Z24V
Current PCB Revision
Binary Coded year (BCD)
Binary Coded week (BCD)
byte 95 = LSB, byte 98 =
MSB
00
64
00
00
00
64
00
00
00
64
00
00
Mosel Vitelic
Revision 2/1.2
SPD Entry Value
14 ns/15 ns/16 ns
-75PC
0E
-75
0F
-10PC
10
29
30
31
32
33
34
35
62-61
15 ns/20 ns
42 ns/45 ns
256 Mbyte
1.5 ns/2.0 ns
0.8 ns/1.0 ns
1.5 ns/2.0 ns
0.8 ns/1.0 ns
0F
2A
40
15
08
15
08
00
14
2D
40
15
08
15
08
00
14
2D
40
20
10
20
10
00
62
63
64
65-71
72
73-90
91-92
93
94
95-98
02
FD
40
00
02
42
40
00
12
B0
40
00
99-125
126
127
128+
Reserved
Intel Specification for Frequency
Reserved
Unused Storage Location
V436632Z24V Rev. 1.1 February 2002
5
MOSEL [ MOSEL VITELIC, CORP ]
