V436632Y24V
E
2
PROM device during module production using a se-
rial presence detect protocol (I
2
C synchronous 2-wire
bus)
A serial presence detect storage device - E
2
PROM -
is assembled onto the module. Information about the
module configuration, speed, etc. is written into the
CILETIV LESO M
Serial Presence Detect Information
SPD-Table for modules:
Byte
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Hex Value
Function Described
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses ( x16 SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (continued)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay from Back to Back Ran-
dom Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency = 2
SPD Entry Value
128
256
SDRAM
13
9
2
64
0
LVTTL
7.5 ns/10.0 ns
5.4 ns/10.0ns
none
Self-Refresh, 7.8
µs
x16
n/a / x16
t
ccd
= 1 CLK
1, 2, 4 & 8
4
CL = 2 / 3
CS Latency = 0
WL = 0
Non Buffered/Non Reg.
Vcc tol ± 10%
7.5 ns/10.0 ns &
Not Supported
7.5ns/10.0ns &
Not Supported
Not Supported
Not Supported
-75PC
80
08
04
0D
09
02
40
00
01
75
54
00
82
10
00
01
-75
80
08
04
0D
09
02
40
00
01
75
54
00
82
10
00
01
-10PC
80
08
04
0D
09
02
40
00
01
A0
60
00
82
10
00
01
16
17
18
19
20
21
22
23
0F
04
06
01
01
00
0E
75
0F
04
06
01
01
00
0E
A0
0F
04
06
01
01
00
0E
A0
24
Maximum Data Access Time from Clock for CL
=2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at CL
=1
Minimum Row Precharge Time
Minimum Row Active to Row Active Delay t
RRD
54
60
60
25
26
00
00
00
00
00
00
27
28
15 ns / 20 ns
14 ns/15 ns/16 ns
0F
0E
14
0F
14
10
V436632Y24V Rev. 1.2 March 2002
4
MOSEL [ MOSEL VITELIC, CORP ]
