V436632R24V(L)
CILETIV LESOM
Byte Num-
ber
28
29
30
31
32
33
34
35
62-61
62
63
64
65-71
72
73-90
91-92
93
94
95-98
99-125
126
127
128+
Reserved
SPD (Continued)Table
Hex Value
Function Described
Minimum Row Active to Row Active Delay
t
RRD
Minimum RAS to CAS Delay t
RCD
Minimum RAS Pulse Width t
RAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
Module Part Number (ASCII)
PCB Identification Code
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
00
64
00
64
00
64
V436632R24V(L)
Mosel Vitelic
Revision 2/1.2
SPD Entry Value
14 ns/15 ns/16 ns
-75PC
0E
-75
0F
-10PC
10
15 ns/20 ns
42 ns/45 ns
128 MByte
1.5 ns/2.0 ns
0.8 ns/1.0 ns
1.5 ns/2.0 ns
0.8 ns/1.0 ns
0F
2A
20
15
08
15
08
00
02
E5
40
00
14
2D
20
15
08
15
08
00
02
2A
40
00
14
2D
20
20
10
20
10
00
12
98
40
00
Intel Specification for Frequency
Supported frequency
Unused Storage Location
00
00
00
DC Characteristics
T
A
= 0°C to 70°C; V
SS
= 0 V; V
DD
, V
DDQ
= 3.3V
±
0.3V
Limit Values
Symbol
V
IH
V
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage (I
OUT
= –2.0 mA)
Output Low Voltage (I
OUT
= 2.0 mA)
Min.
2.0
–0.5
2.4
—
Max.
V
CC
+0.3
0.8
—
0.4
Unit
V
V
V
V
V436632R24V(L) Rev.1.0 October 2001
5
MOSEL [ MOSEL VITELIC, CORP ]
