V436616Y24VATG-75
Serial Presence Detect Information
2
A serial presence detect storage device -
written into the E PROM device during module pro-
2
2
E PROM - is assembled onto the module. Informa-
duction using a serial presence detect protocol (I C
tion about the module configuration, speed, etc. is
synchronous 2-wire bus)
SPD-Table for 75 modules:
Hex Value
Byte Number Function Described
SPD Entry Value
16Mx64
80
0
1
Number of SPD bytes
128
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x16 SDRAM)
Number of DIMM Banks
13
0D
09
4
9
5
1
01
6
Module Data Width
64
40
7
Module Data Width (continued)
Module Interface Levels
0
LVTTL
00
8
01
9
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
7.5 ns
75
10
11
12
13
14
15
5.4 ns
54
none
00
Self-Refresh,7.8 µs
x16
82
SDRAM width, Primary
10
Error Checking SDRAM Data Width
n/a / x16
00
Minimum Clock Delay from Back to Back Random
Column Address
t
ccd = 1 CLK
01
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Burst Length Supported
1, 2, 4, 8
4
0F
04
06
01
01
00
0E
A0
54
00
00
14
0F
14
2D
Number of SDRAM Banks
Supported CAS Latencies
CL =2, 3
CS Latencies
CS Latency = 0
WL = 0
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency = 2
Maximum Data Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at CL = 1
Minimum Row Precharge Time
Minimum Row Active to Row Active Delay tRRD
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Non Buffered/Non Reg.
Vcc tol ± 10%
10. 0 ns
5.4 ns
Not Supported
Not Supported
20 ns
15 ns
20 ns
45 ns
V436616Y24VATG-75 Rev. 1.3 October 2001
4
MOSEL [ MOSEL VITELIC, CORP ]
