V436616R24V(L)
SPD-Table: (Continued)
Hex Value
Byte Number Function Described
SPD Entry Value
128 MByte
1.5 ns
16Mx64
20
31
32
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
15
33
0.8 ns
08
34
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
1.5 ns
15
35
0.8 ns
08
62-61
62
00
Revision 2.0
Mosel Vitelic
02
63
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
29
64
40
65-71
72
00
73-90
91-92
93
Module Part Number (ASCII)
PCB Identification Code
V436616R24V(L)
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
94
95-98
99-125
126
127
128+
Reserved
00
64
8D
00
Intel Specification for Frequency
Supported Features
Unused Storage Location
DC Characteristics
T = 0°C to 70°C; V = 0 V; V , V = 3.3V ± 0.3V
DDQ
A
SS
DD
Limit Values
Symbol Parameter
Min.
2.0
Max.
Unit
V
VIH
VIL
Input High Voltage
Input Low Voltage
VCC+0.3
0.8
–0.5
2.4
V
VOH
VOL
II(L)
Output High Voltage (IOUT = –2.0 mA)
Output Low Voltage (IOUT = 2.0 mA)
Input Leakage Current, any input
—
V
—
0.4
V
–40
40
µA
(0 V < VIN < 3.6 V, all other inputs = 0V)
IO(L)
Output leakage current
–40
40
µA
(DQ is disabled, 0V < VOUT < VCC
)
V436616R24V(L) Rev.1.0 November 2001
5
MOSEL [ MOSEL VITELIC, CORP ]
