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V43658Y04VATG-10PC 参数 Datasheet PDF下载

V43658Y04VATG-10PC图片预览
型号: V43658Y04VATG-10PC
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3伏8M ×64的高性能100兆赫SDRAM SODIMM UNBUFFERED [3.3 VOLT 8M x 64 HIGH PERFORMANCE 100 MHZ SDRAM UNBUFFERED SODIMM]
分类和应用: 内存集成电路动态存储器时钟
文件页数/大小: 11 页 / 161 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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MOSEL VITELIC
AC Characteristics
3,4
T
A
= 0° to 70°C; V
SS
= 0V; V
CC
= 3.3V
±
0.3V, t
T
= 1 ns
V43658Y04VATG-10PC
Limit Values
-10PC
#
Symbol
Parameter
Min.
Max.
Unit
Note
Clock and Clock Enable
1
t
CK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
System frequency
CAS Latency = 3
CAS Latency = 2
Clock Access Time
CAS Latency = 3
CAS Latency = 2
Clock High Pulse Width
Clock Low Pulse Width
Input Setup time
Input Hold Time
CKE Setup Time (Power down mode)
CKE Setup Time (Self Refresh Exit)
Transition time (rise and fall)
10
10
3
3
2
1
2.5
8
1
100
100
6
6
ns
ns
MHz
MHz
4,5
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
6
7
7
8
9
2
f
CK
3
t
AC
4
5
6
7
8
9
10
t
CH
t
CL
t
CS
t
CH
t
CKSP
t
CKSR
t
T
Common Parameters
11
12
13
14
15
16
t
RCD
t
RC
t
RAS
t
RP
t
RRD
t
CCD
RAS to CAS delay
Cycle Time
Active Command Period
Precharge Time
Bank to Bank Delay Time
CAS to CAS delay time
(same bank)
20
70
45
20
16
1
120k
ns
ns
ns
ns
ns
CLK
Refresh Cycle
17
18
t
SREX
t
REF
Self Refresh Exit Time
Refresh Period (4096 cycles)
10
64
ns
ms
9
8
Read Cycle
19
20
21
22
t
OH
t
LZ
t
HZ
t
DQZ
Data Out Hold Time
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
3
0
3
2
9
ns
ns
ns
CLK
10
4
Write Cycle
23
24
25
t
DPL
t
DAL
t
DQW
Data input to Precharge (write recovery)
Data In to Active/refresh
DQM Write Mask Latency
2
5
0
CLK
CLK
CLK
11
V43658Y04VATG-10PC Rev. 1.0 January 2001
7