V43658R04V
SPD (Continued)Table
Hex Value
-75
Byte Num-
ber
Function Described
SPD Entry Value
-75PC
-10PC
28
Minimum Row Active to Row Active Delay
tRRD
14 ns/15 ns/16 ns
0E
0F
10
29
30
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
15 ns/20 ns
42 ns/45 ns
64 MByte
0F
2A
10
15
08
15
08
00
02
D1
40
00
14
2D
10
15
08
15
08
00
02
16
40
00
14
2D
10
20
10
20
10
00
12
84
40
00
31
32
1.5 ns/2.0 ns
0.8 ns/1.0 ns
1.5 ns/2.0 ns
0.8 ns/1.0 ns
33
SDRAM Input Hold Time
34
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
35
62-61
62
Revision 2/1.2
Mosel Vitelic
63
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
64
65-71
72
73-90
91-92
93
Module Part Number (ASCII)
PCB Identification Code
V43658R04V
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
94
95-98
99-125
126
127
128+
Reserved
00
64
00
64
00
64
Intel Specification for Frequency
Supported frequency
Unused Storage Location
00
00
00
DC Characteristics
T = 0°C to 70°C; V = 0 V; V , V = 3.3V ± 0.3V
DDQ
A
SS
DD
Limit Values
Symbol Parameter
Min.
2.0
Max.
Unit
VIH
VIL
Input High Voltage
Input Low Voltage
VCC+0.3
0.8
V
V
V
V
–0.5
2.4
VOH
VOL
Output High Voltage (IOUT = –2.0 mA)
Output Low Voltage (IOUT = 2.0 mA)
—
—
0.4
V43658R04V Rev.1.0 March 2002
5
MOSEL [ MOSEL VITELIC, CORP ]
