V43658R04V
Serial Presence Detect Information
2
A serial presence detect storage device -
written into the E PROM device during module pro-
2
2
E PROM - is assembled onto the module. Informa-
duction using a serial presence detect protocol (I C
tion about the module configuration, speed, etc. is
synchronous 2-wire bus)
SPD Table
Hex Value
Byte Num-
ber
Function Described
Number of SPD bytes
SPD Entry Value
-75PC
80
-75
80
-10PC
80
0
128
256
1
Total bytes in Serial PD
Memory Type
08
08
08
2
SDRAM
12
04
04
04
3
Number of Row Addresses (without BS bits)
0C
0C
09
0C
4
Number of Column Addresses (for x16
SDRAM)
9
09
09
5
6
Number of DIMM Banks
1
01
40
00
01
75
54
00
80
10
00
01
01
40
00
01
75
54
00
80
10
00
01
01
40
00
01
A0
60
00
80
10
00
01
Module Data Width
64
0
7
Module Data Width (continued)
Module Interface Levels
8
LVTTL
9
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
7.5 ns/10.0 ns
5.4 ns/6.0 ns
none
10
11
12
13
14
15
Self-Refresh, 15.6µs
x16
SDRAM width, Primary
Error Checking SDRAM Data Width
n/a / x8
Minimum Clock Delay from Back to Back Ran-
dom Column Address
t
ccd = 1 CLK
16
17
18
19
20
21
22
23
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
1, 2, 4, 8
4
0F
04
06
01
01
00
0E
75
0F
04
06
01
01
00
0E
A0
0F
04
06
01
01
00
0E
A0
CL = 3, 2
CS Latency = 0
WL = 0
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Non Buffered/Non Reg.
Vcc tol ± 10%
Minimum Clock Cycle Time at CAS Latency =
2
7.5 ns/10.0 ns
24
Maximum Data Access Time from Clock for
CL = 2
5.4 ns/6.0 ns
54
60
60
25
26
Minimum Clock Cycle Time at CL = 1
Not Supported
Not Supported
00
00
00
00
00
00
Maximum Data Access Time from Clock at CL
= 1
27
Minimum Row Precharge Time
15 ns/20 ns
0F
14
14
V43658R04V Rev. 1.0 March 2002
4
MOSEL [ MOSEL VITELIC, CORP ]
