MOSEL VITELIC
SPD-Table: (Continued)
V436532S04VATG-10PC
Hex Value
Byte
Number
30
31
32
33
34
35
36-61
62
63
64-125
Function Described
Minimum RAS Pulse Width t
RAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
Checksum for Bytes 0 - 62
Manufacturers’s Information (Optional)
(FFh if not used)
Max. Frequency Specification
100 MHz Support Details
Unused Storage Location
SPD Entry Value
45 ns
128 MByte
2 ns
1 ns
2 ns
1 ns
100 MHz
-10PC
2D
20
20
10
20
10
00
Revision 1.2
12
FD
126
127
128+
100 MHz
64
FF
00
T
A
= 0
°
C to 70
°
C; V
SS
= 0 V; V
DD
, V
DDQ
= 3.3V
±
0.3V
Limit Values
Symbol
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
DC Characteristics
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage (I
OUT
= –2.0 mA)
Output Low Voltage (I
OUT
= 2.0 mA)
Input Leakage Current, any input
(0 V < V
IN
< 3.6 V, all other inputs = 0V)
Output leakage current
(DQ is disabled, 0V < V
OUT
< V
CC
)
Min.
2.0
–0.5
2.4
—
–40
Max.
V
CC
+0.3
0.8
—
0.4
40
Unit
V
V
V
V
µ
A
µ
A
–40
40
V436532S04VATG-10PC Rev. 1.0 February 2001
5
MOSEL [ MOSEL VITELIC, CORP ]
