MOSEL VITELIC
V436416S04V(C)TG-10PC
SPD-Table: (Continued)
Hex Value
100 MHz
-10PC
2D
10
Byte
Number Function Described
SPD Entry Value
30
31
Minimum RAS Pulse Width t
45 ns
64 MByte
2 ns
RAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
32
20
33
SDRAM Input Hold Time
1 ns
10
34
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
Superset Information (May be used in Future)
SPD Revision
2 ns
20
35
1 ns
10
36-61
62
00
Revision 1.2
100 MHz
12
63
Checksum for Bytes 0 - 62
FD
XX
64-125
Manufacturers’s Information (Optional)
(FFh if not used)
126
127
Max. Frequency Specification
100 MHz Support Details
Unused Storage Location
64
AF
00
128+
DC Characteristics
T = 0°C to 70°C; V = 0 V; V , V = 3.3V ± 0.3V
A
SS
DD
DDQ
Limit Values
Symbol Parameter
Min.
2.0
Max.
Unit
V
V
V
V
V
Input High Voltage
Input Low Voltage
Output High Voltage (I
V
+0.3
IH
CC
–0.5
2.4
0.8
V
IL
= –2.0 mA)
= 2.0 mA)
—
0.4
40
V
OH
OL
OUT
OUT
Output Low Voltage (I
—
V
I
Input Leakage Current, any input
–40
µA
I(L)
(0 V < V < 3.6 V, all other inputs = 0V)
IN
I
Output leakage current
–40
40
µA
O(L)
(DQ is disabled, 0V < V
< V
)
OUT
CC
V436416S04V(C)TG-10PC Rev. 1.2 June 2000
5