MOSEL VITELIC
Table 2. Command Codes
First Bus
Program Cycle
Command
Sequence
Read
Read
Autoselect
Address
XXXXH
5555H
5555H
Data
F0H
AAH
AAH
2AAAH
2AAAH
55H
55H
5555H
5555H
F0H
90H
RA(1)
00H
01H
Byte
Program
Chip Erase
5555H
AAH
2AAAH
55H
5555H
A0H
PA
RD(2)
40H(6)
82H(7)
PD(4)
Second Bus
Program Cycle
Address
Data
Third Bus
Program Cycle
Address
Data
Fourth Bus
Program Cycle
Address
Data
Fifth Bus
Program Cycle
Address
Data
V29LC51002
Six Bus
Program Cycle
Address
Data
5555H
AAH
AAH
2AAAH
2AAAH
55H
55H
5555H
5555H
80H
80H
5555H
5555H
AAH
AAH
2AAAH
2AAAH
55H
55H
5555H
SA(5)
10H
30H
Sector Erase 5555H
NOTES:
1. RA: Read Address
2. RD: Read Data
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.
5. SA(5): Sector Address
6. 40H: Manufacturing ID
7. 82H: Device ID
Chip Erase Cycle
The V29LC51002 features a chip-erase
operation. The chip erase operation is initiated by
using a specific six-bus-cycle sequence: two unlock
program cycles, a setup command, two additional
unlock program cycles, and the chip erase
command (see Table 2).
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and is completed in 3 sec max.
V29LC51002 Rev. 0.5 October 2000
9
MOSEL [ MOSEL VITELIC, CORP ]
