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V29C51004T-90T 参数 Datasheet PDF下载

V29C51004T-90T图片预览
型号: V29C51004T-90T
PDF下载: 下载PDF文件 查看货源
内容描述: X8闪存EEPROM\n [x8 Flash EEPROM ]
分类和应用: 闪存可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 15 页 / 70 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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MO SEL VITELIC  
V29C51004T/V29C51004B  
Functional Description  
V29C51004T  
V29C51004B  
The V29C51004T/V29C51004B consists of 512  
equally-sized sectors of 1K bytes each. The 16 KB  
lockable Boot Block is intended for storage of the  
system BIOS boot code. The boot code is the first  
piece of code executed each time the system is  
powered on or rebooted.  
7FFFFH  
16KB Boot Block  
1 KB  
1 KB  
7C000H  
1 KB  
The V29C51004 is available in two versions: the  
V29C51004T with the Boot Block address starting  
from 7C000H to 7FFFFH, and the V29C51004B  
with the Boot Block address starting from 00000H  
to 3FFFFH.  
1 KB  
1 KB  
03FFFH  
16KB Boot Block  
1 KB  
00000H  
00000H  
Read Cycle  
51004-15  
A read cycle is performed by holding both CE  
and OE signals LOW. Data Out becomes valid only  
when these conditions are met. During a read cycle  
WE must be HIGH prior to CE and OE going LOW.  
WE must remain HIGH during the read operation  
for the read to complete (see Table 1).  
16KB Boot Block = 32 Sectors  
Byte Write Cycle  
The V29C51004T/V29C51004B is programmed  
on a byte-by-byte basis. The byte write operation is  
initiated by using a specific four-bus-cycle  
sequence: two unlock program cycles, a program  
setup command and program data program cycles  
(see Table 2).  
During the byte write cycle, addresses are  
latched on the falling edge of either CE or WE,  
whichever is last. Data is latched on the rising edge  
of CE or WE, whichever is first. The byte write cycle  
can be CE controlled or WE controlled.  
Output Disable  
Returning OE or CE HIGH, whichever occurs first  
will terminate the read operation and place the l/O  
pins in the HIGH-Z state.  
Standby  
The device will enter standby mode when the CE  
signal is HIGH. The l/O pins are placed in the  
HIGH-Z, independent of the OE input state.  
Sector Erase Cycle  
The V29C51004T/V29C51004B features a  
sector erase operation which allows each sector to  
be erased and reprogrammed without affecting  
data stored in other sectors. Sector erase operation  
is initiated by using a specific six-bus-cycle  
sequence: Two unlock program cycles, a setup  
command, two additional unlock program cycles,  
and the sector erase command (see Table 2). A  
sector must be first erased before it can be re-  
Command Sequence  
The V29C51004T/V29C51004B does not  
provide the resetfeature to return the chip to its  
normal state when an incomplete command  
sequence or an interruption has happened. In this  
case, normal operation (Read Mode) can be  
restored by issuing a non-existentcommand  
sequence, for example Address: 5555H, Data FFH.  
Table 1. Operation Modes Decoding  
Decoding Mode  
Read  
CE  
OE  
WE  
A
A
A
I/O  
READ  
PD  
0
0
0
1
1
1
9
9
9
V
V
V
V
IH  
A
A
A
A
A
A
IL  
IL  
IH  
IL  
Byte Write  
V
V
IH  
IL  
Standby  
V
X
X
X
X
X
HIGH-Z  
CODE  
CODE  
X
Autoselect Device ID  
Autoselect Manufacture ID  
Enabling Boot Block Protection Lock  
Disabling Boot Block Protection Lock  
Output Disable  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IL  
IL  
IL  
IL  
IL  
IH  
IH  
IH  
IL  
IL  
H
H
H
H
V
IL  
V
V
V
V
X
X
H
H
IL  
IL  
IH  
V
X
X
X
X
X
H
V
V
V
X
HIGH-Z  
IL  
IH  
NOTES:  
1. X = Dont Care, V = HIGH, V = LOW, V = 12.5V Max.  
IH  
IL  
H
2. PD: The data at the byte address to be programmed.  
V29C51004T/V29C51004B Rev. 1.5 October 2000  
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