MO SEL VITELIC
V29C51002T/V29C51002B
Table 2. Command Codes
First Bus
Program Cycle
Second Bus
Program Cycle
Third Bus
Program Cycle
Fourth Bus
Program Cycle
Fifth Bus
Program Cycle
Six Bus
Program Cycle
Command
Sequence
Address Data Address Data Address Data Address Data
Address Data Address Data
Read
Read
XXXXH
5555H
5555H
F0H
AAH 2AAAH
AAH 2AAAH
55H
55H
5555H
5555H
F0H RA(1)
RD(2)
See table 3 for detail.
Autoselect
Mode
90H
Byte
5555H
5555H
AAH 2AAAH
55H
5555H
A0H PA
PD(4)
Program
Chip Erase
AAH 2AAAH
AAH 2AAAH
55H
55H
5555H
5555H
80H
80H
5555H
5555H
AAH
AAH
2AAAH
2AAAH
55H
55H
5555H
SA(5)
10H
30H
Sector Erase 5555H
NOTES:
1. RA: Read Address
2. RD: Read Data
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.
5. SA(5): Sector Address
and the sector erase command (see Table 2). A
sector must be first erased before it can be re-
written. While in the internal erase mode, the
device ignores any program attempt into the
device. The internal erase completion can be
determined via DATA polling or toggle bit status.
The V29C51002T/V29C51002B is shipped fully
erased (all bits = 1).
data, and the device is then ready for the next
cycle.
Toggle Bit (I/O )
6
The V29C51002T/V29C51002B also features
another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O toggling between 1 and 0. Once the program is
6
Chip Erase Cycle
completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.
The V29C51002T/V29C51002B features a chip-
erase operation. The chip erase operation is
initiated by using a specific six-bus-cycle
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is “1”.
Boot Block Protection Enabling/Disabling
The V29C51002T/V29C51002B features
hardware Boot Block Protection. The boot block
sector protection is enabled when high voltage
(12.5V) is applied to OE and A9 pins with CE pin
LOW and WE pin LOW. The sector protection is
disabled when high voltage is applied to OE, CE
and A9 pins with WE pin LOW. Other pins can be
HIGH or LOW. This is shown in table 1.
Program Cycle Status Detection
There are two methods for determining the state
of the V29C51002T/V29C51002B during a
Autoselect Mode
program (erase/write) cycle: DATA Polling (I/O )
7
The V29C51002T/V29C51002B features an
Autoselect mode to identify boot block locking
status, device ID and manufacturer ID.
and Toggle Bit (I/O ).
6
DATA Polling (I/O )
7
The V29C51002T/V29C51002B features DATA
polling to indicate the end of a program cycle.
When the device is in the program cycle, any
attempt to read the device will received the
Entering Autoselect mode is accomplished by
applying a high voltage (VH) to the A9 Pin, or
through a sequence of commands (as shown in
table 2). Device will exit this mode once high
voltage on A9 is removed or another command is
loaded into the device.
complement of the loaded data on I/O . Once the
7
program cycle is completed, I/O will show true
7
V29C51002T/V29C51002B Rev. 2.1 October 2000
10
MOSEL [ MOSEL VITELIC, CORP ]
