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V29C51001T 参数 Datasheet PDF下载

V29C51001T图片预览
型号: V29C51001T
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位131,072 ×8位的5伏CMOS FLASH MEMORY [1 MEGABIT 131,072 x 8 BIT 5 VOLT CMOS FLASH MEMORY]
分类和应用:
文件页数/大小: 16 页 / 77 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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MO SEL VITELIC  
V29C51001T/V29C51001B  
Functional Description  
V29C51001T  
V29C51001B  
The V29C51001T/V29C51001B consists of 256  
equally-sized sectors of 512 bytes each. The 8 KB  
lockable Boot Block is intended for storage of the  
system BIOS boot code. The boot code is the first  
piece of code executed each time the system is  
powered on or rebooted.  
The V29C51001 is available in two versions: the  
V29C51001T with the Boot Block address starting  
from 1E000H to 1FFFFH, and the V29C51001B  
with the Boot Block address starting from 00000H  
to 1FFFFH.  
1FFFFH  
512  
8KB Boot Block  
1E000H  
512  
512  
512  
512  
512  
512  
512  
01FFFH  
8KB Boot Block  
00000H  
00000H  
Read Cycle  
51001-13  
A read cycle is performed by holding both CE  
and OE signals LOW. Data Out becomes valid only  
when these conditions are met. During a read cycle  
WE must be HIGH prior to CE and OE going LOW.  
WE must remain HIGH during the read operation  
for the read to complete (see Table 1).  
8KB Boot Block = 16 Sectors  
sequence or an interruption has happened. In this  
case, normal operation (Read Mode) can be  
restored by issuing a non-existentcommand  
sequence, for example Address: 5555H, Data FFH.  
Output Disable  
Byte Program Cycle  
Returning OE or CE HIGH, whichever occurs first  
will terminate the read operation and place the l/O  
pins in the HIGH-Z state.  
The V29C51001T/V29C51001B is programmed  
on a byte-by-byte basis. The byte program  
operation is initiated by using a specific four-bus-  
cycle sequence: two unlock program cycles, a  
program setup command and program data  
program cycles (see Table 2).  
During the byte program cycle, addresses are  
latched on the falling edge of either CE or WE,  
whichever is last. Data is latched on the rising edge  
of CE or WE, whichever is first. The byte program  
cycle can be CE controlled or WE controlled.  
Standby  
The device will enter standby mode when the CE  
signal is HIGH. The l/O pins are placed in the  
HIGH-Z, independent of the OE signal.  
Command Sequence  
The V29C51001T/V29C51001B does not  
provide the resetfeature to return the chip to its  
normal state when an incomplete command  
Table 1. Operation Modes Decoding  
Decoding Mode  
Read  
CE  
OE  
WE  
A
A
A
I/O  
READ  
PD  
0
0
0
1
1
1
9
9
9
V
V
V
IH  
A
A
A
A
A
A
IL  
IL  
IH  
IL  
Byte Write  
V
V
V
IH  
IL  
Standby  
V
X
X
X
X
X
HIGH-Z  
CODE  
CODE  
X
Autoselect Device ID  
Autoselect Manufacture ID  
Enabling Boot Block Protection Lock  
Disabling Boot Block Protection Lock  
Output Disable  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IL  
IL  
IL  
IL  
IL  
IH  
IH  
IH  
IL  
IL  
H
H
H
H
V
IL  
V
V
V
V
X
X
H
IL  
IL  
IH  
V
X
X
X
X
X
H
H
V
V
V
X
HIGH-Z  
IL  
IH  
NOTES:  
1. X = Dont Care, V = HIGH, V = LOW. V = 12.5V Max.  
IH  
IL  
H
2. PD: The data at the byte address to be programmed.  
V29C51001T/V29C51001B Rev. 0.8 October 2000  
9
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