MO SEL VITELIC
V29C51001T/V29C51001B
Table 2. Command Codes
First Bus
Program Cycle
Second Bus
Program Cycle
Third Bus
Program Cycle
Fourth Bus
Program Cycle
Fifth Bus
Program Cycle
Six Bus
Program Cycle
Command
Sequence
Address Data Address Data Address Data Address Data
Address Data Address Data
Read
XXXXH
5555H
5555H
F0H
Read
AAH 2AAAH
AAH 2AAAH
55H
55H
5555H
5555H
F0H RA
RD
Autoselect
90H
00H
01H
40H
01H
(1)
(2)
A1H
Byte
5555H
5555H
AAH 2AAAH
55H
5555H
A0H PA
PD(4)
Program
Chip Erase
AAH 2AAAH
AAH 2AAAH
55H
55H
5555H
5555H
80H
80H
5555H
5555H
AAH
AAH
2AAAH
2AAAH
55H
55H
5555H
PA(3)
10H
30H
Sector Erase 5555H
NOTES:
1. Top Boot Sector
2. Bottom Boot Sector
3. PA: The address of the memory location to be programmed.
4. PD: The data at the byte address to be programmed.
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is “1”.
Sector Erase Cycle
The V29C51001T/V29C51001B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. Sector erase operation
is initiated by using a specific six-bus-cycle
sequence: Two unlock program cycles, a setup
command, two additional unlock program cycles,
and the sector erase command (see Table 2). A
sector must be first erased before it can be
reprogrammed. While in the internal erase mode,
the device ignores any program attempt into the
device. The internal erase completion can be
determined via DATA polling or toggle bit.
Program Cycle Status Detection
There are two methods for determining the state
of the V29C51001T/V29C51001B during a
program (erase/program) cycle: DATA Polling
(I/O ) and Toggle Bit (I/O ).
7
6
DATA Polling (I/O )
7
The V29C51001T/V29C51001B features DATA
polling to indicate the end of a program cycle.
When the device is in the program cycle, any
attempt to read the device will received the
The V29C51001T/V29C51001B is shipped with
pre-erased sectors (all bits = 1).
complement of the loaded data on I/O . Once the
7
program cycle is completed, I/O will show true
7
data, and the device is then ready for the next
cycle.
Chip Erase Cycle
The V29C51001T/V29C51001B features a chip-
erase operation. The chip erase operation is
initiated by using a specific six-bus-cycle
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).
The chip erase operation is performed
sequentially, one sector at a time. When the
automated on chip erase algorithm is requested
with the chip erase command sequence, the device
automatically programs and verifies the entire
memory array for an all zero pattern prior to erasure
Toggle Bit (I/O )
6
The V29C51001T/V29C51001B also features
another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O toggling between 1 and 0. Once the program is
6
completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.
V29C51001T/V29C51001B Rev. 0.8 October 2000
10
MOSEL [ MOSEL VITELIC, CORP ]
