MOSEL VITELIC
MS7200L/7201AL/7202AL
256 x 9, 512 x 9, 1K x 9
CMOS FIFO
Descriptions
MS7200L/7201AL/7202AL
Features
s
First-In/First-Out static RAM based dual port
memory
s
Three densities in a x9 configuration
s
Low power versions
s
Includes empty, full, and half full status flags
s
Direct replacement for industry standard
Mostek and IDT
s
Ultra high-speed 30 MHz FIFOs available with
33 ns cycle times.
s
Fully expandable in both depth and width
s
Simultaneous and asynchronous read and write
s
Auto retransmit capability
s
TTL compatible interface, single 5V ± 10%
power supply
s
Available in 28 pin 300 mil and 600 mil plastic
DIP, 32 Pin PLCC and 330 mil SOG
Pin Configurations
28-PIN PDIP
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
V
CC
D4
D5
D6
D7
FL / RT
RS
EF
The MS7200L/7201AL/7202AL are dual-port
static RAM based CMOS First-In/First-Out (FIFO)
memories organized in nine-bit wide words. The
devices are configured so that data is read out in
the same sequential order that it was written in.
Additional expansion logic is provided to allow for
unlimited expansion of both word size and depth.
The dual-port RAM array is internally sequenced
by independent Read and Write pointers with no
external addressing needed. Read and write
operations are fully asynchronous and may occur
simultaneously, even with the device operating at
full speed. Status flags are provided for full, empty,
and half-full conditions to eliminate data underflow
and overflow. The x9 architecture provides an
additional bit which may be used as a parity or
control bit. In addition, the devices offer a retransmit
capability which resets the Read pointer and allows
for retransmission from the beginning of the data.
The MS7200L/7201AL/7202AL are available in a
range of frequencies from 10 to 30 MHz (33 - 100 ns
cycle times). A low power version with a 500µA
power down supply current is available. They are
manufactured on Mosel-Vitelic’s high performance
1.2µ CMOS process and operate from a single 5V
power supply.
300 mil
600 mil
DIP
&
330 mil
SOG
Block Diagram
DATA INPUTS (Q0-Q8)
22
21
20
19
18
17
16
15
XO / HF
Q7
Q6
Q5
Q4
R
W
WRITE
CONTROL
WRITE
POINTER
RAM
ARRAY
256x9
512x9
1Kx9
READ
POINTER
32-PIN PLCC
VCC
THREE
STATE
BUFFERS
DATA OUTPUTS (Q0-Q8)
29
28
27
26
25
24
23
22
21
D6
D7
NC
FL / RT
RS
EF
XO / HF
Q7
Q6
NC
D3
D8
D4
4
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
5
8
7
8
9
10
11
14
13
3
2
1 32 31 30
D5
W
R
READ
CONTROL
RESET
LOGIC
FLAG
LOGIC
EF
HF
FF
RS
FL / RT
32 Pin PLCC
Top View
14 15 16 17 18 19 20
VSS
NC
XI
EXPANSION
LOGIC
Q8
R
Q4
Q3
Q5
XO
MS7200L/01AL/02AL Rev. 1.0 January 1995
1
MOSEL [ MOSEL VITELIC, CORP ]
