ISSUE 4.2 : November 1998
PUMA 68F4006/A-70/90/12
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target systems. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally a desired system design practice.
The device contains an autoselect operation to supplement traditional PROM programming methodology. The
operation is initiated by writing the autoselect command sequence into the command register. Following the
command write, a read cycle from address XX00H retrieves the manufacture code of 01H. A read cycle from
address XX01H returns the device code 20H. All manufacturer and device codes will exhibit odd parity with the
MSB (D7) defined as the parity bit.
Furthermore, the write protect status of sectors can be read in this mode, scanning the sector addresses (A14,
A15 & A16) while (A1, A0) = (1, 0) will produce a logical '1' at device output DQ0 for a protected sector.
To terminate the operation, it is necessary to write the read/reset command sequence into the register.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
"unlock" write cycle. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of WE/WE1-4 or CE1-4, whichever happens later, while the data are latched on the
rising edge of WE/WE1-4 or CE1-4 whichever happens first. The rising edge of WE/WE1-4 or CE1-4 begins
programming. Upon executing the Embedded Program Algorithm Command sequence the system is not
required to provide further controls or timings. The device will automatically provide adequate internally gener-
ated program pulses and verify the programmed cell margin. The automatic programming operation is com-
pleted when the data on D7 is equivalent to data written to this bit (see written Operations Status) at which time
the device returns to read mode. Data Polling must be performed at the memory location which is being
programmed.
Programming is allowed in any address sequence and across sector boundaries.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase. The systems is not required to provide any controls or timings during
these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on D7 is "1" (See Written Operation Section) at which time the device returns to read the mode.
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MOSAIC [ MOSAIC ]
